公开(公告)号：US20240321700A1

公开(公告)日：2024-09-26

申请号：US18612492

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeyeun Choi ,  Taeho Ko ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/498 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49811 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/22 ,  H01L2224/81

Abstract: A semiconductor package includes an upper redistribution structure, a first substrate, a first semiconductor chip, a second semiconductor chip, a bridge chip, and a first insulating layer. The upper redistribution structure includes an upper redistribution insulating layer and upper redistribution patterns. The first substrate includes an upper surface, a lower surface, a first cavity extending in a vertical direction, and a second cavity provided apart from the first cavity in a horizontal direction and extending in the vertical direction. The first substrate is on an upper surface of the upper redistribution structure. The first semiconductor chip is accommodated in the first cavity and electrically connected to a subset of the upper redistribution patterns. The second semiconductor chip is accommodated in the second cavity and electrically connected to a subset of the upper redistribution patterns. The bridge chip is below the upper redistribution structure. The first insulating layer surrounds the bridge chip.

公开(公告)号：US10985091B2

公开(公告)日：2021-04-20

申请号：US16691910

申请日：2019-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyeun Choi ,  Jaemok Jung ,  Eunjin Kim ,  Chilwoo Kwon

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/522

Abstract: This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.