公开(公告)号：US09336877B2

公开(公告)日：2016-05-10

申请号：US14504914

申请日：2014-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yun Lee ,  Sun Woo-Jung ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C8/08 ,  G11C13/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C13/0026 ,  G11C13/004 ,  G11C2211/5623 ,  G11C2213/71

Abstract: A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.

Abstract translation: 非易失性存储器件利用可变电阻元件。 非易失性存储器件包括多个存储体，并且布置成跨越多个存储体的第一至第三写入全局位线。 多个存储体中的每一个包括使用电阻材料的多个非易失性存储单元。 第一，第二和第三写全局位线按顺序彼此直接相邻布置。 当在写入周期期间向第一写入全局位线提供写入电流时，固定的电压被施加到第二写入全局位线，而第三个全局位线被浮置。

公开(公告)号：US09659644B2

公开(公告)日：2017-05-23

申请号：US14612640

申请日：2015-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Jeong ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Jae-Yun Lee

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.

公开(公告)号：US09570168B2

公开(公告)日：2017-02-14

申请号：US14832229

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/418 ,  G11C11/417 ,  G11C7/10

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。

公开(公告)号：US20160055905A1

公开(公告)日：2016-02-25

申请号：US14832229

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Woo-Jung Sun ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2213/71 ,  G11C2213/72

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。