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1.发明授权公开(公告)号：US12189976B2
公开(公告)日：2025-01-07
申请号：US18506293
申请日：2023-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-Hoon Woo , Hak-Sun Kim , Kwang-Jin Lee , Su-Chang Jeon
Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.
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公开(公告)号：US10606511B2
公开(公告)日：2020-03-31
申请号：US15297562
申请日：2016-10-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwang-Jin Lee
Abstract: A nonvolatile memory module including a plurality of memory chips, a spare chip, and a module controller may be provided. The plurality of memory chips may be disposed on a printed circuit board (PCB), and each of the plurality of memory chips may include a plurality of nonvolatile memory cells. The spare chip may be disposed on the PCB and includes a plurality of nonvolatile memory cells. The spare chip may perform different functions according to operation modes of the plurality of memory chips. The module controller may disposed on the PCB, and control operations of the plurality of memory chips and the spare chip.
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公开(公告)号：US09336877B2
公开(公告)日：2016-05-10
申请号：US14504914
申请日：2014-10-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Yun Lee , Sun Woo-Jung , Kwang-Jin Lee , Dong-Hoon Jeong , Beak-Hyung Cho
CPC classification number: G11C13/0069 , G11C7/02 , G11C7/1006 , G11C7/18 , G11C13/0026 , G11C13/004 , G11C2211/5623 , G11C2213/71
Abstract: A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.
Abstract translation: 非易失性存储器件利用可变电阻元件。 非易失性存储器件包括多个存储体，并且布置成跨越多个存储体的第一至第三写入全局位线。 多个存储体中的每一个包括使用电阻材料的多个非易失性存储单元。 第一，第二和第三写全局位线按顺序彼此直接相邻布置。 当在写入周期期间向第一写入全局位线提供写入电流时，固定的电压被施加到第二写入全局位线，而第三个全局位线被浮置。
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4.发明申请MEMORY SYSTEMS THAT SUPPORT READ RECLAIM OPERATIONS AND METHODS OF OPERATING SAME TO THEREBY PROVIDE REAL TIME DATA RECOVERY 审中-公开支持读取记录操作的记忆系统和操作方法，以提供实时数据恢复公开(公告)号：US20150355845A1
公开(公告)日：2015-12-10
申请号：US14729518
申请日：2015-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwang-Jin Lee , Seonghun Kim , Jeong-Han Kim , Sunghee Lee , Sanggyu Jang , Hong Suk Choi
IPC: G06F3/06
CPC classification number: G06F3/0679 , G06F3/0616 , G06F3/0659 , G06F12/0246 , G11C16/3418 , G11C16/349 , G11C16/3495 , G11C2211/5641
Abstract: Methods of operating nonvolatile memory devices include counting a number of consecutive read operations performed on a first memory region within the nonvolatile memory device, and executing a page reclaim operation on the first memory region in response to detecting that a count in the number of consecutive read operations meets or exceeds a threshold count. A page reclaim operation may include checking an error bit level within a page of data stored in a multi-level cell block within the memory device. The page reclaim operation may further include moving page data from the multi-level cell block to a single-level cell block in the memory device and error correcting the page data during the moving.
Abstract translation: 操作非易失性存储器件的方法包括对在非易失性存储器件内的第一存储器区域执行的连续读取操作的数量进行计数，以及响应于检测到连续读取数量的计数，对第一存储器区域执行页面回收操作 操作满足或超过阈值计数。 页面回收操作可以包括检查存储在存储器设备内的多级单元块中的数据页内的错误位级别。 页面回收操作可以进一步包括将页面数据从多级单元块移动到存储器件中的单级单元块，并且在移动期间纠错页面数据。
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5.发明授权公开(公告)号：US11003382B2
公开(公告)日：2021-05-11
申请号：US16503116
申请日：2019-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-hoon Woo , Hak-sun Kim , Kwang-Jin Lee , Su-chang Jeon
Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.
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Patent Agency Ranking
公开(公告)号：US09799399B2
公开(公告)日：2017-10-24
申请号：US15298765
申请日：2016-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwang-Jin Lee
CPC classification number: G11C13/0069 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C5/04 , G11C11/005 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/004 , G11C13/0061 , G11C13/0097 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.
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7.发明授权Nonvolatile memory device with reduced coupling noise and driving method thereof 有权具有降低耦合噪声的非易失性存储器件及其驱动方法公开(公告)号：US09570168B2
公开(公告)日：2017-02-14
申请号：US14832229
申请日：2015-08-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Yun Lee , Woo-Jung Sun , Kwang-Jin Lee , Dong-Hoon Jeong , Beak-Hyung Cho
IPC: G11C7/00 , G11C13/00 , G11C11/418 , G11C11/417 , G11C7/10
CPC classification number: G11C13/004 , G11C7/1075 , G11C7/20 , G11C11/417 , G11C11/418 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2207/2209 , G11C2207/2281 , G11C2207/229 , G11C2213/71 , G11C2213/72
Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.
Abstract translation: 提供了非易失性存储器件和非易失性存储器件的驱动方法。 非易失性存储器件可以包括多个存储器组，由多个存储器组共享的读取全局位线，由多个存储器组共享的写入全局位线，与读取的全局位线连接的读取电路，并执行 读取操作和与写入全局位线连接的放电控制电路，并且在上电操作之后的初始化间隔期间主要对写入全局位线进行放电。
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公开(公告)号：US08724400B2
公开(公告)日：2014-05-13
申请号：US13948138
申请日：2013-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC: G11C16/04
CPC classification number: G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。
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9.发明申请公开(公告)号：US20190140022A1
公开(公告)日：2019-05-09
申请号：US16135315
申请日：2018-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： JI-HYUN JEONG , Dae-Hwan Kang , Du-Eung Kim , Kwang-Jin Lee
Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.
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10.发明授权Method of operating nonvolatile memory device comprising resistance material 有权包括电阻材料的非易失性存储器件的操作方法公开(公告)号：US09405615B2
公开(公告)日：2016-08-02
申请号：US14278354
申请日：2014-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung Sunwoo , Kwang-Jin Lee
CPC classification number: G06F11/10 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C29/021 , G11C29/028 , G11C2013/0054 , G11C2013/0057 , G11C2029/0409 , G11C2029/0411
Abstract: A method of operating a nonvolatile memory device comprises applying a read current with a first level to a nonvolatile memory cell comprising a variable resistance material, determining read data based on the applied read current, checking a syndrome corresponding to the read data to determine whether the read data is pass or fail, changing the read current from the first level to a second level, which is different from the first level, according to the determination of whether the read data is pass or fail, and performing a read-retry operation comprising applying the read current of the second level to the nonvolatile memory cell.
Abstract translation: 一种操作非易失性存储器件的方法包括将具有第一电平的读取电流施加到包括可变电阻材料的非易失性存储器单元，基于所应用的读取电流确定读取数据，检查与所读取的数据相对应的校正子，以确定是否 读取数据通过或失败，根据所读取的数据是否通过的确定，将读取的电流从第一电平改变到与第一电平不同的第二电平，并执行读取重试操作，包括 将第二级的读取电流施加到非易失性存储单元。
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