公开(公告)号：US20130286741A1

公开(公告)日：2013-10-31

申请号：US13926297

申请日：2013-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Ku KANG

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Abstract translation: 提供闪存器件和读取方法，其中存储器单元被分成至少两组。 根据阈值电压分布选择存储单元。 根据第一读取操作，检测存储在所选择的存储器单元中的数据并且对应于至少两个组中的一个锁存数据。 第二读取操作检测并锁存与至少两个组中的另一组对应的存储单元的数据。 在第二次读取操作期间通过软判决算法处理数据。

公开(公告)号：US20170017582A1

公开(公告)日：2017-01-19

申请号：US15183319

申请日：2016-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Ku KANG

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2221/2105 ,  G06F2221/2111

Abstract: In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

Abstract translation: 在一个实施例中，数据存储装置包括：控制单元，被配置为对至少一个输入命令进行解码，并被配置为响应于输入命令产生读取信号和起始信号中的至少一个。 起始信号指示开始内部模式确定处理。 数据存储装置还包括被配置为响应于读取信号而输出数据的存储单元，以及编码单元，被配置为响应于起始信号启动和执行内部模式确定处理。 内部模式确定处理包括自主确定编码模式，并且编码单元被配置为基于所确定的编码模式对输出数据进行编码以产生编码数据。

公开(公告)号：US20130294158A1

公开(公告)日：2013-11-07

申请号：US13936857

申请日：2013-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Jin KONG ,  Sung Chung PARK ,  Dong-Ku KANG ,  Young Hwan LEE ,  Si Hoon HONG ,  Jae Woong HYUN

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract translation: 多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。 在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。 在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。 从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。