公开(公告)号：US20250023522A1

公开(公告)日：2025-01-16

申请号：US18602326

申请日：2024-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kibaek KWON ,  Donghyuk LIM ,  Youngho CHOI

IPC: H03F1/42 ,  H03F3/45

Abstract: An amplification circuit includes an amplifier comprising an input terminal and an output terminal, a first inductor unit connected to the input terminal, and a second inductor unit connected to the output terminal. The first inductor unit and the second inductor unit may be inductively coupled to each other so that a change in output voltage of the amplification circuit is positively fed back.

公开(公告)号：US20230146174A1

公开(公告)日：2023-05-11

申请号：US17981086

申请日：2022-11-04

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Wook KIM ,  Soonwon KWON ,  Inhwan SONG ,  Beomkyu SEO ,  Donghyuk LIM

IPC: G06F30/27

CPC classification number: G06F30/27 ,  G06F2113/18

Abstract: A method for modeling a serializer/deserializer (SerDes) model includes generating plural data sets including noise simulation data of the SerDes model and output measurement data of an actual SerDes, training a machine learning model based on the plural data sets, and applying the trained machine learning model and an estimation model to a model included in the SerDes model. The estimation model provides the noise simulation data as an input to the trained machine learning model.

公开(公告)号：US20240178845A1

公开(公告)日：2024-05-30

申请号：US18514975

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngho CHOI ,  Donghyuk LIM ,  Kibaek KWON

IPC: H03K21/00 ,  H03K5/13 ,  H03K5/24 ,  H03K19/21

CPC classification number: H03K21/00 ,  H03K5/13 ,  H03K5/24 ,  H03K19/21

Abstract: An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

公开(公告)号：US20190386775A1

公开(公告)日：2019-12-19

申请号：US16257249

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： June-Hee LEE ,  Donghyuk LIM

IPC: H04L1/00 ,  H04L25/03 ,  H03M13/41 ,  H03M13/00

Abstract: A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.

公开(公告)号：US20190058576A1

公开(公告)日：2019-02-21

申请号：US15960686

申请日：2018-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghyuk LIM

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0334 ,  H03L7/00 ,  H03L7/0991 ,  H04L7/0037 ,  H04L7/0331 ,  H04L7/0337

Abstract: A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.