公开(公告)号：US20230041850A1

公开(公告)日：2023-02-09

申请号：US17967733

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit,a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

公开(公告)号：US20180089087A1

公开(公告)日：2018-03-29

申请号：US15349949

申请日：2016-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Dongyan Jiang ,  Hongzhong Zheng

IPC: G06F12/0862 ,  G06F12/0868

CPC classification number: G06F12/0862 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/6022 ,  G06F2212/6026

Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.

公开(公告)号：US11269811B2

公开(公告)日：2022-03-08

申请号：US16595441

申请日：2019-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Qiang Peng ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F16/174 ,  G06F11/14 ,  G06F16/22 ,  G06F16/215

Abstract: A memory system is disclosed. The memory system may include a Big Hash Table and a Little Hash Table. The memory system may also include an Overflow Region and a Translation Table to map a logical address to a Physical Line Identifier (PLID), which may include a region identifier and a physical address.

公开(公告)号：US11126354B2

公开(公告)日：2021-09-21

申请号：US16735688

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F12/0831 ,  G06F9/46 ,  G06F12/1009 ,  G06F12/0868 ,  G06F13/28

Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

公开(公告)号：US11079954B2

公开(公告)日：2021-08-03

申请号：US16180002

申请日：2018-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Qiang Peng ,  Andrew Chang ,  Hongzhong Zheng

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/46

Abstract: A deduplication memory system includes a virtual memory space, a physical memory space and a memory manager. The memory manager generates a user data entry that is stored in the physical memory space. The user data entry represents a unique user data of a predetermined granularity appearing in the virtual memory space, and includes first and second portions. The first portion includes information relating to a number of duplication times the unique user data corresponding to the user data entry is duplicated in the virtual memory space, and the second portion includes a selected part of the unique user data from which the unique user data may be reconstructed. The first portion may include an index to an extended reference counter table or a special data pattern table if the number of duplication times of the unique user data is greater than or equal to a predetermined number.

公开(公告)号：US20180217777A1

公开(公告)日：2018-08-02

申请号：US15473311

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Changhui Lin ,  Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/0656 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/10 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/65 ,  G06F2213/16

Abstract: A memory module includes a host interface configured to provide an interface to a host computer; one or more memory devices; a deduplication engine configured to provide a virtual memory capacity of the memory module that is larger than a physical size of the one or more memory devices; a memory controller for controlling access to the one or more memory devices; a volatile memory comprising a hash table, an overflow memory region, and a credit unit, wherein the overflow memory region stores user data when a hash collision occurs or the hash table is full, and wherein the credit unit stores an address of an invalidated entry in the overflow memory region; and a control logic is configured to control the overflow memory region and the credit unit and generate a warning indicating a status of the overflow memory region and the credit unit.

公开(公告)号：US11475102B2

公开(公告)日：2022-10-18

申请号：US16407064

申请日：2019-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

公开(公告)号：US10528284B2

公开(公告)日：2020-01-07

申请号：US15498371

申请日：2017-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Changhui Lin ,  Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

IPC: G06F3/06

Abstract: A dedupe module is provided. The dedupe module includes: a host interface; a dedupe engine to receive a data request from a host system via the host interface; a memory controller; a plurality of memory modules, each memory module being coupled to the memory controller; and a read cache for caching data from the memory controller for use by the dedupe engine.

公开(公告)号：US10268413B2

公开(公告)日：2019-04-23

申请号：US15473311

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Changhui Lin ,  Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

Abstract: A memory module includes a host interface configured to provide an interface to a host computer; one or more memory devices; a deduplication engine configured to provide a virtual memory capacity of the memory module that is larger than a physical size of the one or more memory devices; a memory controller for controlling access to the one or more memory devices; a volatile memory comprising a hash table, an overflow memory region, and a credit unit, wherein the overflow memory region stores user data when a hash collision occurs or the hash table is full, and wherein the credit unit stores an address of an invalidated entry in the overflow memory region; and a control logic is configured to control the overflow memory region and the credit unit and generate a warning indicating a status of the overflow memory region and the credit unit.

公开(公告)号：US20170286313A1

公开(公告)日：2017-10-05

申请号：US15476757

申请日：2017-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Changhui Lin ,  Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

IPC: G06F12/1018 ,  G06F12/0864 ,  G06F3/06

Abstract: A method of retrieving data stored in a memory associated with a dedupe module is provided. The method includes: identifying a logical address of the data; identifying a physical line ID of the data in accordance with the logical address by looking up at least a portion of the logical address in a translation table; locating a respective physical line, the respective physical line corresponding to the PLID; and retrieving the data from the respective physical line, the retrieving including copying a respective hash cylinder to the read cache, the respective hash cylinder including: a respective hash bucket, the respective hash bucket including the respective physical line; and a respective reference counter bucket, the respective reference counter bucket including a respective reference counter associated with the respective physical line.