公开(公告)号：US20250038108A1

公开(公告)日：2025-01-30

申请号：US18630248

申请日：2024-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk HWANG

IPC: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes a substrate having a pair of second conductive lines thereon, and a first conductive line extending between the pair of second conductive lines and the substrate. A contact plug extends between the pair of second conductive lines and is electrically connected to the first conductive line. A gate electrode extends on the contact plug. First and second semiconductor patterns extend on first and second ones of the pair of second conductive lines, respectively. A gate insulating pattern extends between each of the first and second semiconductive patterns and the gate electrode. The first conductive line may be configured as a word line, and the pair of second conductive lines may be configured as a pair of bit lines. The gate electrode may be configured as a gate electrode of a first access transistor within a first DRAM cell and as a gate electrode of a second access transistor within a second DRAM cell.

公开(公告)号：US20240074157A1

公开(公告)日：2024-02-29

申请号：US18336340

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk HWANG ,  Sanghoon UHM ,  Minhee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05

Abstract: A semiconductor device may include a bit line on a substrate, a gate electrode over the bit line and spaced apart from the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel on a sidewall of the gate insulation pattern and including an oxide semiconductor material, a conductive pattern contacting an upper surface of the channel and including an amorphous oxide semiconductor material, and a contact plug contacting an upper surface of the conductive pattern. The contact plug may include a metal. The amorphous oxide semiconductor material may include fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H), or argon (Ar).

公开(公告)号：US20220190242A1

公开(公告)日：2022-06-16

申请号：US17395043

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejung KIM ,  Taehong MIN ,  Chorong PARK ,  Joohee SEO ,  Eunsuk HWANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.