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    SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME
    2.
    发明申请
    SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME 有权
    分离门型非易失性存储器件，具有嵌入式分离型非易失性存储器件的半导体器件及其形成方法

    公开(公告)号：US20130242659A1

    公开(公告)日：2013-09-19

    申请号：US13743445

    申请日：2013-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

    IPC: H01L29/788 ,  G11C16/04

    CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

    Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

    Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

    METHOD OF PREVENTING PROGRAM-DISTURBANCES FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    METHOD OF PREVENTING PROGRAM-DISTURBANCES FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    防止非易失性半导体存储器件的程序障碍的方法

    公开(公告)号：US20140043896A1

    公开(公告)日：2014-02-13

    申请号：US13939611

    申请日：2013-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Weon-Ho Park ,  Hyok-Ki Kwon ,  Min-Sup Kim ,  Min-Su Kim ,  Byoung-Ho Kim ,  Eui-Yeol Kim ,  Sang-Hoon Park ,  Ji-Hoon Park ,  Min-Jee Sung ,  Hyo-Soung Sim ,  Chang-Min Jeon ,  Hee-Seog Jeon

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/3427

    Abstract: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.

    Abstract translation: 提供一种防止具有多个存储单元的非易失性半导体存储器件的程序干扰的方法，每个存储单元中的每一个包括选择晶体管和串联耦合在位线和公共源极线之间的存储晶体管。 当选择的存储器单元被选择为为了选择存储单元时，与所选存储单元共享第一选择行的第一非选择存储单元和不与所选存储单元共享第一选择行的第二未选择存储单元 在存储单元之间进行编程。 当所选择的存储单元通过向耦合到所选存储单元的第一选择线施加正电压来编程时，将负电压施加到耦合到第二未选择存储单元的第二选择线。

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