公开(公告)号：US11588054B2

公开(公告)日：2023-02-21

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20250098278A1

公开(公告)日：2025-03-20

申请号：US18815956

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Moon ,  Donghoon Hwang ,  Hyojin Kim ,  Kyunghee Cho

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.

公开(公告)号：US20240321991A1

公开(公告)日：2024-09-26

申请号：US18503019

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingeon Hwang ,  Jinbum Kim ,  Hyojin Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Taehyung Lee

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.

公开(公告)号：US20250107178A1

公开(公告)日：2025-03-27

申请号：US18643104

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Donghoon Hwang ,  Hyojin Kim ,  Byungho Moon ,  Doyoung Choi

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.

公开(公告)号：USD1041433S1

公开(公告)日：2024-09-10

申请号：US29851736

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Designer： Hyojin Kim ,  Jaehyung Kim

Abstract: FIG. 1 is a front perspective view of a portable television set, showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof; and,
FIG. 8 is a rear perspective view thereof.
The broken lines illustrating portions of the portable television set form no part of the claimed design.

公开(公告)号：US20240258328A1

公开(公告)日：2024-08-01

申请号：US18416473

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon HWANG ,  Inchan Hwang ,  Hyojin Kim

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1266

Abstract: An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

公开(公告)号：US11631670B2

公开(公告)日：2023-04-18

申请号：US17509239

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jihye Lee ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/161

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

公开(公告)号：US10289831B2

公开(公告)日：2019-05-14

申请号：US15168536

申请日：2016-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul Lee ,  Hyojin Kim ,  Jae-Wook Lee ,  Sooyoung Woo ,  Kyu-Sam Lee

IPC: H04L9/06 ,  G06F21/44 ,  H04L9/32 ,  H04W12/12 ,  H04W88/02 ,  H04W12/10

Abstract: A display driver integrated circuit includes a seed generation block configured to generate a seed, an encryption block configured to encrypt the seed and generate a first encryption text, and a comparison block configured to receive a second encryption text, in which the seed is encrypted, from an application processor, compare the first encryption text with the second encryption text, and output a control signal based on the comparison result.

公开(公告)号：US12288805B2

公开(公告)日：2025-04-29

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US12159938B2

公开(公告)日：2024-12-03

申请号：US17711914

申请日：2022-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Sangmoon Lee ,  Jinbum Kim ,  Yongjun Nam

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.