公开(公告)号：US11626401B2

公开(公告)日：2023-04-11

申请号：US16991530

申请日：2020-08-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  Ilgyou Shin ,  Seunghun Lee

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/02

摘要： An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US20180219010A1

公开(公告)日：2018-08-02

申请号：US15937093

申请日：2018-03-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： CHANGHWA KIM ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L27/02

CPC分类号： H01L27/0886 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US09825153B2

公开(公告)日：2017-11-21

申请号：US15422907

申请日：2017-02-02

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

公开(公告)号：US20230006052A1

公开(公告)日：2023-01-05

申请号：US17656023

申请日：2022-03-23

申请人： Samsung Electronics Co., Ltd.

发明人： HAEJUN YU ,  Kyungin Choi ,  Sungmin Kim ,  Seunghun Lee ,  Jinbum Kim

IPC分类号： H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417

摘要： A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.

公开(公告)号：US10804269B2

公开(公告)日：2020-10-13

申请号：US16419318

申请日：2019-05-22

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungin Choi ,  Taehyeon Kim ,  Hongshik Shin ,  Taegon Kim ,  Jaeyoung Park ,  Yuichiro Sasaki

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L21/285

摘要： A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US10355000B2

公开(公告)日：2019-07-16

申请号：US15793442

申请日：2017-10-25

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungin Choi ,  Taehyeon Kim ,  Hongshik Shin ,  Taegon Kim ,  Jaeyoung Park ,  Yuichiro Sasaki

IPC分类号： H01L27/092 ,  H01L21/82 ,  H01L21/768 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

摘要： A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US10002788B2

公开(公告)日：2018-06-19

申请号：US15145924

申请日：2016-05-04

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungin Choi ,  Jaeran Jang ,  Yoonhae Kim

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/3115 ,  H01L29/165

CPC分类号： H01L21/76825 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

摘要： Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

申请人： Samsung Electronics Co., Ltd.

发明人： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC分类号： H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

摘要： A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11380760B2

公开(公告)日：2022-07-05

申请号：US17028042

申请日：2020-09-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungin Choi ,  Hyunchul Song ,  Sunjung Kim ,  Taegon Kim ,  Seong Hoon Jeong

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/78 ,  H01L29/423

摘要： A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20220068920A1

公开(公告)日：2022-03-03

申请号：US17524128

申请日：2021-11-11

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC分类号： H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

摘要： Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.