公开(公告)号：US11056432B2

公开(公告)日：2021-07-06

申请号：US16451944

申请日：2019-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US11887968B2

公开(公告)日：2024-01-30

申请号：US17493975

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong ,  Tae Hun Kim ,  Hyuek Jae Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

公开(公告)号：US20210296228A1

公开(公告)日：2021-09-23

申请号：US17338815

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US11776916B2

公开(公告)日：2023-10-03

申请号：US17199703

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon Park ,  Young Min Lee ,  Dae-Woo Kim ,  Hyuek Jae Lee

IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US11088038B2

公开(公告)日：2021-08-10

申请号：US16508498

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Tae Hun Kim ,  Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong

IPC: H01L23/528 ,  H01L21/66 ,  H01L23/00

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

公开(公告)号：US20240096728A1

公开(公告)日：2024-03-21

申请号：US18340101

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Kyeong Seol ,  Hyuek Jae Lee

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L23/3107 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor package is provided. The semiconductor package comprises a first semiconductor die including a memory, a second semiconductor die including a memory and on the first semiconductor die, a dummy die on the semiconductor device and not including a memory, a heat sink on the dummy die and including a metal material and a mold film on side surfaces of each of the first semiconductor die, the second semiconductor die, the dummy die, and the heat sink. A width of the heat sink may decrease away from a top surface of the dummy die, and side surfaces of the heat sink may be curved.

公开(公告)号：US11887900B2

公开(公告)日：2024-01-30

申请号：US17367903

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Tae Hun Kim ,  Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong

IPC: H01L23/528 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/5283 ,  H01L24/09

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

公开(公告)号：US11581257B2

公开(公告)日：2023-02-14

申请号：US17338815

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US11145626B2

公开(公告)日：2021-10-12

申请号：US16589541

申请日：2019-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong ,  Tae Hun Kim ,  Hyuek Jae Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.