公开(公告)号：US20240120318A1

公开(公告)日：2024-04-11

申请号：US18312331

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Don Mun ,  Sang Cheon Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/5226 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.

公开(公告)号：US11508685B2

公开(公告)日：2022-11-22

申请号：US16992895

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US11694996B2

公开(公告)日：2023-07-04

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Un-Byoung Kang ,  Sang Cheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/13 ,  H01L24/20 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/1302 ,  H01L2224/214 ,  H01L2225/06541

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

公开(公告)号：US10121731B2

公开(公告)日：2018-11-06

申请号：US15290899

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon Park ,  Won Il Lee ,  Chajea Jo ,  Taeje Cho

IPC: H01L23/48 ,  H01L23/13 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

公开(公告)号：US11776916B2

公开(公告)日：2023-10-03

申请号：US17199703

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon Park ,  Young Min Lee ,  Dae-Woo Kim ,  Hyuek Jae Lee

IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US20230076511A1

公开(公告)日：2023-03-09

申请号：US18054530

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US12261164B2

公开(公告)日：2025-03-25

申请号：US18480310

申请日：2023-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

公开(公告)号：US11955449B2

公开(公告)日：2024-04-09

申请号：US18054530

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L24/03 ,  H01L24/08 ,  H01L24/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/08146 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US11798929B2

公开(公告)日：2023-10-24

申请号：US17381985

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Hyuekjae Lee ,  Taehun Kim

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.