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公开(公告)号：US20220139948A1
公开(公告)日：2022-05-05
申请号：US17377848
申请日：2021-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Il Gweon KIM , Hyun Cheol KIM , Hyeoung Won SEO , Sung Won YOO , Jae Ho HONG
IPC: H01L27/11578 , H01L27/11565
Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
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公开(公告)号：US20210335798A1
公开(公告)日：2021-10-28
申请号：US17227793
申请日：2021-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Hyun Cheol KIM , Satoru YAMADA , Sung Won YOO , Jae Ho HONG
IPC: H01L27/1156 , H01L27/11524 , H01L27/11529 , H01L27/11548 , H01L27/11551
Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
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Patent Agency Ranking
公开(公告)号：US20240357810A1
公开(公告)日：2024-10-24
申请号：US18757708
申请日：2024-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Il Gweon KIM , Hyun Cheol KIM , Hyeoung Won SEO , Sung Won YOO , Jae Ho HONG
Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
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公开(公告)号：US20130091887A1
公开(公告)日：2013-04-18
申请号：US13650621
申请日：2012-10-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok Jun SON , Sung Cheol KANG , Hyun Cheol KIM
Abstract: A relay module includes a case forming an exterior of the relay module, a Positive Temperature Coefficient (PTC) device configured to control the supply of power to the compressor, a holder mounted at the case and configured to accommodate the PTC device, a start capacitor electrically connected to the PTC device, a first connecting terminal having a first PTC connecting terminal connected to the PTC device and a first capacitor connecting terminal connected to the start capacitor, and a second connecting terminal having a second PTC connecting terminal connected to the PTC device and a second capacitor connecting terminal connected to the start capacitor. The first capacitor connecting terminal and the second capacitor connecting terminal are spaced apart a predetermined distance from a bottom surface of the case.
Abstract translation: 继电器模块包括形成继电器模块的外部的壳体，配置成控制向压缩机供电的正温度系数（PTC）装置，安装在壳体处并被配置为容纳PTC装置的保持器，启动电容器 电连接到PTC装置，具有连接到PTC装置的第一PTC连接端子和连接到起动电容器的第一电容器连接端子的第一连接端子和具有连接到PTC装置的第二PTC连接端子的第二连接端子 以及连接到起动电容器的第二电容器连接端子。 第一电容器连接端子和第二电容器连接端子与壳体的底表面隔开预定的距离。
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公开(公告)号：US20240047550A1
公开(公告)日：2024-02-08
申请号：US18182426
申请日：2023-03-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki Heun LEE , Yong Seok KIM , Hyun Cheol KIM , Dae Won HA
IPC: H01L29/51 , H01L29/417 , H01L29/78
CPC classification number: H01L29/516 , H01L29/41725 , H01L29/78391
Abstract: Provided are semiconductor devices. The semiconductor device includes a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction, extending in a third direction, and penetrating the gate structure, wherein the active pattern includes a two-dimensional material, the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer, which are sequentially stacked on the active pattern, the gate insulating layer includes hexagonal boron nitride (h-BN), and the ferroelectric layer includes a bilayer of a two-dimensional material.
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公开(公告)号：US20230269501A1
公开(公告)日：2023-08-24
申请号：US18086449
申请日：2022-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeong Soon KANG , Hyun Cheol KIM , Woo Bin SONG , Kyung Hwan LEE
IPC: H04N25/77 , H04N25/709
CPC classification number: H04N25/77 , H04N25/709
Abstract: An image sensor includes a photoelectric converter configured to convert received light into charges in response to the received light and provide the charges to a first node, a transfer transistor configured to provide a voltage of the first node to a floating diffusion node, a reset transistor configured to reset a voltage of the floating diffusion node to a driving voltage based on a reset signal, a source follower transistor configured to provide a unit pixel output based on the voltage of the floating diffusion node, a select transistor connected to the source follower transistor and gated with a selection signal to output the unit pixel output to the outside, and a ferroelectric capacitor connected to the floating diffusion node, wherein the ferroelectric capacitor is configured to adjust a conversion gain of the floating diffusion node based on a conversion gain mode of the ferroelectric capacitor, the conversion gain mode being a first conversion gain mode, a second conversion gain mode, or a third conversion gain mode.
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公开(公告)号：US20210319293A1
公开(公告)日：2021-10-14
申请号：US17224575
申请日：2021-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Hyun Cheol KIM , Satoru YAMADA , Sung Won YOO , Jae Ho HONG
Abstract: A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.
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