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    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN
    3.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN 有权

    公开(公告)号：US20210358913A1

    公开(公告)日：2021-11-18

    申请号：US17092593

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L27/102 ,  H01L29/74

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE STRUCTURE 有权

    公开(公告)号：US20210074914A1

    公开(公告)日：2021-03-11

    申请号：US16592041

    申请日：2019-10-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Tae Hun KIM ,  Seok Han PARK ,  Satoru YAMADA ,  Jae Ho HONG

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210225842A1

    公开(公告)日：2021-07-22

    申请号：US16999378

    申请日：2020-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L27/102 ,  H01L29/24

    Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210036020A1

    公开(公告)日：2021-02-04

    申请号：US16942093

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Han PARK ,  Yong Seok KIM ,  Hui-Jung KIM ,  Satoru YAMADA ,  Kyung Hwan LEE ,  Jae Ho HONG ,  Yoo Sang HWANG

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L29/78

    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

    SEMICONDUCTOR DEVICE INCLUDING DUMMY METAL
    9.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DUMMY METAL 审中-公开
    包含金属的半导体器件

    公开(公告)号：US20170005100A1

    公开(公告)日：2017-01-05

    申请号：US15139444

    申请日：2016-04-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min Hee CHO ,  Satoru YAMADA ,  Sung-Sam LEE ,  Jung-Bun LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10897 ,  H01L23/522 ,  H01L23/5226

    Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

    Abstract translation: 半导体器件可以包括形成在不同垂直级别的基板上的电浮置的多个虚拟布线和多个虚拟接触插塞，每个虚拟接触插头电连接在多个虚拟布线中的多个虚拟布线的两个相邻的虚拟布线之间。 多个虚拟布线的虚拟布线不与基板中包含的多个晶体管中的任一个晶体管的端子电连接。

    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
    具有盖式结构的半导体器件及其制造方法

    公开(公告)号：US20160240619A1

    公开(公告)日：2016-08-18

    申请号：US15011820

    申请日：2016-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

    IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

    CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

    Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

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