公开(公告)号：US20240196593A1

公开(公告)日：2024-06-13

申请号：US18225798

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonyoung JEONG ,  Hyungjun NOH ,  Sangho LEE ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a bottom surface of the substrate, a first active pattern on the bit line, a first word line intersecting the first active pattern in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction, and a first conductive pattern on the first active pattern. The first word line includes a first side surface facing the first direction. The first active pattern includes a first portion between the first word line and the first conductive pattern, a second portion between the first word line and the bit line, and a third portion extending on the first side surface of the first word line to connect the first portion to the second portion of the first active pattern.

公开(公告)号：US20230320066A1

公开(公告)日：2023-10-05

申请号：US17951379

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonyoung JEONG ,  Kiseok LEE ,  Hyungeun CHOI ,  Hyungjun NOH ,  Sangho LEE

IPC: H01L27/108

CPC classification number: H01L27/10805

Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.

公开(公告)号：US20200381436A1

公开(公告)日：2020-12-03

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun NOH ,  Junsoo KIM ,  Dongsoo WOO ,  Namho JEON

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/51 ,  H01L21/265 ,  H01L21/3115

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.