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    SEMICONDUCTOR MEMORY DEVICES
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230180456A1

    公开(公告)日：2023-06-08

    申请号：US18059492

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euichul JEONG ,  Kiseok LEE ,  Wonki ROH ,  Hyungeun CHOI

    IPC: H10B12/00

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

    Abstract: A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240431122A1

    公开(公告)日：2024-12-26

    申请号：US18623732

    申请日：2024-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Incheol NAM

    IPC: H10B80/00 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210125989A1

    公开(公告)日：2021-04-29

    申请号：US16986367

    申请日：2020-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240421039A1

    公开(公告)日：2024-12-19

    申请号：US18652381

    申请日：2024-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungeun CHOI ,  Kiseok LEE

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: A semiconductor device includes a lower chip structure including a memory structure and a lower wiring structure connected to the memory structure and an upper chip structure on the lower chip structure, where the upper chip structure includes an upper base, peripheral transistors below the upper base, an intermediate wiring structure below the upper base and connected to the peripheral transistors, an upper wiring structure on the upper base, a first through-via penetrating the upper base between the upper wiring structure and the intermediate wiring structure, the first through-via connecting the upper wiring structure and the intermediate wiring structure, and a second through-via extending respectively downward and penetrating the upper base between the upper wiring structure and the lower wiring structure, the second through-via connecting the upper wiring structure and the lower wiring structure.

    SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230320066A1

    公开(公告)日：2023-10-05

    申请号：US17951379

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moonyoung JEONG ,  Kiseok LEE ,  Hyungeun CHOI ,  Hyungjun NOH ,  Sangho LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10805

    Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.

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