公开(公告)号：US20190289664A1

公开(公告)日：2019-09-19

申请号：US16352122

申请日：2019-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsung KHO ,  Kyuho HAN ,  Joonseo LEE ,  Moonyoung JEONG ,  Giwon LEE

IPC: H04W76/34 ,  H04W92/06 ,  H04W76/32

Abstract: A method of a first terminal is provided. The method includes communicating with a first gateway by using a first internet protocol (IP) address allocated to the first terminal, according to a first IP session, in response to a distance between the first terminal and a second gateway being equal to or less than a predetermined threshold, establishing a second IP session with the second gateway while the first IP session is set in the first terminal, receiving, from a second terminal, a first IP session-release message about the first IP session via the second gateway by using a second IP address according to the second IP session, when data from the first terminal is received by the second terminal according to the first IP session, and in response to the first IP session-release message being received from the second gateway, releasing the first IP session with the first gateway.

公开(公告)号：US20240130108A1

公开(公告)日：2024-04-18

申请号：US18369552

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euichul JEONG ,  Sang-Woon LEE ,  Sangho LEE ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20210037597A1

公开(公告)日：2021-02-04

申请号：US16965757

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsung KHO ,  Moonyoung JEONG ,  Jaehyun HWANG ,  Joonseo LEE ,  Kyuho HAN

IPC: H04W80/10 ,  H04W76/12 ,  H04W72/04

Abstract: Provided is a method of establishing a session for communication with a local network in a wireless communication system, the method including obtaining a request for using an integrated mode in which a user plane entity of a base station uses an integrated user plane entity that performs an operation of a user plane function (UPF) together, when a session between a local network and a user equipment (UE) is established, determining based on user information of the UE whether to accept use of an integrated mode, selecting the integrated user plane entity as a user plane entity in which the session is to be established, based on a result of the determining, and transmitting a session establishment request to the selected integrated user plane entity.

公开(公告)号：US20160240619A1

公开(公告)日：2016-08-18

申请号：US15011820

申请日：2016-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

公开(公告)号：US20240268129A1

公开(公告)日：2024-08-08

申请号：US18370940

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jay-Bok CHOI ,  Hyungeun CHOI ,  Jinwoo HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

公开(公告)号：US20230352548A1

公开(公告)日：2023-11-02

申请号：US18219525

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae CHO ,  Dongjin LEE ,  Ji Eun LEE ,  Kyoung-Ho JUNG ,  Dong Su KO ,  Yongsu KIM ,  Jiho YOO ,  Sung HEO ,  Hyun PARK ,  Satoru YAMADA ,  Moonyoung JEONG ,  Sungjin KIM ,  Gyeongsu PARK ,  Han Jin LIM

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

公开(公告)号：US20210029515A1

公开(公告)日：2021-01-28

申请号：US16641572

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuho HAN ,  Young-Sung KHO ,  Joonseo LEE ,  Moonyoung JEONG ,  Giwon LEE

IPC: H04W4/08 ,  H04W76/12 ,  H04W76/11

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure is to provide a multicast service in a wireless communication system and comprises the steps of: receiving a multicast group participation message transmitted from a terminal via a communication session from a terminal to a first network entity; generating a multicast tunnel generation request message on the basis of the multicast group participation message, and transmitting the same to the first network entity; and generating a multicast service request message on the basis of the multicast group participation message, and transmitting the same to a second network entity. The present research is research that has been conducted with the support of the “Cross-Departmental Giga KOREA Project” funded by the government (the Ministry of Science and ICT) in 2017 (No. GK17N0100, millimeter wave 5G mobile communication system development).

公开(公告)号：US20190198626A1

公开(公告)日：2019-06-27

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/84

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20240196593A1

公开(公告)日：2024-06-13

申请号：US18225798

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonyoung JEONG ,  Hyungjun NOH ,  Sangho LEE ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a bottom surface of the substrate, a first active pattern on the bit line, a first word line intersecting the first active pattern in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction, and a first conductive pattern on the first active pattern. The first word line includes a first side surface facing the first direction. The first active pattern includes a first portion between the first word line and the first conductive pattern, a second portion between the first word line and the bit line, and a third portion extending on the first side surface of the first word line to connect the first portion to the second portion of the first active pattern.