公开(公告)号：US20240196593A1

公开(公告)日：2024-06-13

申请号：US18225798

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonyoung JEONG ,  Hyungjun NOH ,  Sangho LEE ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a bottom surface of the substrate, a first active pattern on the bit line, a first word line intersecting the first active pattern in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction, and a first conductive pattern on the first active pattern. The first word line includes a first side surface facing the first direction. The first active pattern includes a first portion between the first word line and the first conductive pattern, a second portion between the first word line and the bit line, and a third portion extending on the first side surface of the first word line to connect the first portion to the second portion of the first active pattern.

公开(公告)号：US20230225117A1

公开(公告)日：2023-07-13

申请号：US17862638

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok HONG ,  Sung-Jin YEO ,  Yoongi HONG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: A semiconductor device includes a substrate including cell and core regions respectively having first and second active patterns having respective, opposing sidewall surfaces at least partially defining a trench therebetween, and a boundary region between the cell and core regions, a device isolation layer on the boundary region to fill the trench, a line structure on the first active pattern and extended from the cell region to the boundary region, and a capping pattern covering an end of the line structure on the boundary region. The device isolation layer includes one or more inner surfaces at least partially defining a recess region, which is adjacent to the end of the line structure, and the capping pattern is extended along the end of the line structure into the recess region. A top surface of the device isolation layer is between the line structure and a bottom surface of the capping pattern.

公开(公告)号：US20240334677A1

公开(公告)日：2024-10-03

申请号：US18480389

申请日：2023-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho LEE ,  Moonyoung JEONG ,  Ilgweon KIM ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a bit line, first and second word lines spaced apart from each other on the bit line, a back gate electrode between the first and second word lines, a first active pattern between the first word line and the back gate electrode, a second active pattern between the second word line and the back gate electrode, contact patterns connected to the first and second active patterns, respectively, and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line. A top surface of the first gate insulating pattern is located at substantially a same height as top surfaces of the first and second word lines. The first gate insulating pattern includes a high-k dielectric material.

公开(公告)号：US20240040772A1

公开(公告)日：2024-02-01

申请号：US18332413

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyoung LEE ,  Sungjin YEO ,  Wonseok YOO ,  Jaemin WOO ,  Kyeongock CHONG ,  Myunghun JUNG ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device may include a bit line structure, a first spacer, and a second spacer on a substrate. The bit line structure may include a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate. The first spacer and the second spacer may be stacked in a horizontal direction on a sidewall of the bit line structure. The horizontal direction may be substantially parallel to the upper surface of the substrate. The conductive structure may include a nitrogen-containing conductive portion at a lateral portion thereof. The first spacer may contact the nitrogen-containing conductive portion.