公开(公告)号：US20170162434A1

公开(公告)日：2017-06-08

申请号：US15250199

申请日：2016-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook OH ,  Jong-Hyun LEE ,  Sung-Wook HWANG

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/033

CPC classification number: H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76813 ,  H01L21/76816 ,  H01L22/20 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

公开(公告)号：US20240282763A1

公开(公告)日：2024-08-22

申请号：US18650982

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Wook OH ,  Byungyun KANG ,  Donghyun KIM ,  Hyungjune KIM ,  Jaebong JUNG

IPC: H01L27/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/481 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via.

公开(公告)号：US20220139900A1

公开(公告)日：2022-05-05

申请号：US17329669

申请日：2021-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Wook OH ,  Byungyun KANG ,  Donghyun KIM ,  Hyungjune KIM ,  Jaebong JUNG

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/48 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via.