公开(公告)号：US20180040669A1

公开(公告)日：2018-02-08

申请号：US15485594

申请日：2017-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhe WU ,  Jeong Hee PARK ,  Dong Ho AHN ,  Jin Woo LEE ,  Hee Ju SHIN ,  Ja Bin LEE

IPC: H01L27/24 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22 ,  H01L45/00 ,  H01L43/02

CPC classification number: H01L27/2427 ,  H01L23/528 ,  H01L27/224 ,  H01L27/2481 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

公开(公告)号：US20200152264A1

公开(公告)日：2020-05-14

申请号：US16530517

申请日：2019-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Zhe WU ,  Ja Bin LEE ,  Jin Woo LEE ,  Kyu Bong JUNG

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.

公开(公告)号：US20200091234A1

公开(公告)日：2020-03-19

申请号：US16386893

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Zhe WU ,  Kyubong JUNG ,  Seung-geun YU ,  Ja Bin LEE

IPC: H01L27/24 ,  H01L45/00

Abstract: A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.