公开(公告)号：US10199389B2

公开(公告)日：2019-02-05

申请号：US15485334

申请日：2017-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US09646984B2

公开(公告)日：2017-05-09

申请号：US15264902

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US08972811B2

公开(公告)日：2015-03-03

申请号：US14094195

申请日：2013-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Sik Kang ,  Jae-Goo Lee

IPC: G06F11/00 ,  G01R31/3183 ,  G09G3/00 ,  G09G3/36 ,  H04N5/06 ,  H04N17/04 ,  G09G5/00

CPC classification number: G01R31/318378 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3648 ,  G09G5/006 ,  G09G2330/02 ,  G09G2340/125 ,  H04N5/06 ,  H04N17/04

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

公开(公告)号：US09634024B2

公开(公告)日：2017-04-25

申请号：US14642086

申请日：2015-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Chung-Jin Kim ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee ,  Moo-Rym Choi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

公开(公告)号：US20140089753A1

公开(公告)日：2014-03-27

申请号：US14094195

申请日：2013-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Sik Kang ,  Jae-Goo Lee

IPC: G01R31/3183

CPC classification number: G01R31/318378 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3648 ,  G09G5/006 ,  G09G2330/02 ,  G09G2340/125 ,  H04N5/06 ,  H04N17/04

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract translation: 提供了产生面板测试图案的面板驱动电路和测试面板的方法。 驱动电路包括图案生成单元和选择单元。 图案生成单元响应系统时钟并产生模式测试数据和模式测试信号。 选择单元响应于测试信号，并且选择并输出（a）从模式生成单元输出的模式测试数据和模式测试信号，或者（b）直接应用的模式测试数据和模式测试信号 从外部。 驱动电路和面板测试方法使用系统时钟产生驱动电路内的面板测试数据，水平同步信号，垂直同步信号和数据激活信号，从而可以执行面板的测试 而不使用单独的测试设备。