METHOD OF OPERATING MEMORY DEVICE
    1.
    发明申请
    METHOD OF OPERATING MEMORY DEVICE 有权
    操作存储器件的方法

    公开(公告)号:US20140129903A1

    公开(公告)日:2014-05-08

    申请号:US14069588

    申请日:2013-11-01

    Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

    Abstract translation: 一种操作存储器件的方法包括将确定第一电压状态或第二电压状态的第一读取电压改变为第一范围内的电压并将电压确定为第一选择读取电压,并且改变第二读取电压 ,其用于确定存储在存储单元中的数据是否是第三不同电压状态或第四不同电压状态,以及第二不同范围内的电压,并将电压确定为第二选择读取电压。 第一电压状态与第二电压重叠。 第三电压状态与第四电压状态重叠。 第三和第四电压状态的交点处的电压与第二读取电压之间的差异大于第一和第二电压状态与第一读取电压的交点处的电压之间的差。

    APPARATUS AND METHOD OF OPERATING MEMORY DEVICE
    2.
    发明申请
    APPARATUS AND METHOD OF OPERATING MEMORY DEVICE 有权
    装置和操作存储器件的方法

    公开(公告)号:US20140129902A1

    公开(公告)日:2014-05-08

    申请号:US14068122

    申请日:2013-10-31

    Abstract: A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

    Abstract translation: 可与存储器系统一起使用的存储装置包括电压发生器到多个第一候选电压和多个第二候选电压,以及X解码器,以顺序地施加多个第一候选电压中的每一个,并且多个第二候选 电压到存储单元阵列的一个或多个单元,然后分别施加多个第一候选电压和多个第二候选电压中的一个作为第一读取电压和第二电压以从 根据存储单元阵列的单元的特性,存储单元阵列的单元。

    NONVOLATILE MEMORY SYSTEM
    3.
    发明申请
    NONVOLATILE MEMORY SYSTEM 审中-公开
    非易失性存储系统

    公开(公告)号:US20130185609A1

    公开(公告)日:2013-07-18

    申请号:US13668607

    申请日:2012-11-05

    CPC classification number: G06F11/0751

    Abstract: A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.

    Abstract translation: 提供非易失性存储器系统。 非易失性存储器件包括多级存储器阵列和页缓冲器; 以及存储器控制器,被配置为控制要从多级存储器阵列读取并存储在页缓冲器中的第一页数据,要检测的第一页数据的第一错误位,存储在第一页数据中的第一页数据的错误 使用在第一误差位中校正的误差的第一校正数据进行校正的页面缓冲器以及要对多级存储器阵列执行的经纠错的第一页数据的第一刷新程序操作。

    MEMORY DEVICE INCLUDING NAND STRINGS AND METHOD OF OPERATING THE SAME

    公开(公告)号:US20190035466A1

    公开(公告)日:2019-01-31

    申请号:US16035958

    申请日:2018-07-16

    Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

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