公开(公告)号：US20180151236A1

公开(公告)日：2018-05-31

申请号：US15664180

申请日：2017-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Soo PARK

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5625 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.

公开(公告)号：US20190035466A1

公开(公告)日：2019-01-31

申请号：US16035958

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Dong KIM ,  Tae-Hyun KIM ,  Sang-Wan NAM ,  Sang-Soo PARK ,  Jae-Yong JEONG

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

公开(公告)号：US20150179238A1

公开(公告)日：2015-06-25

申请号：US14468936

申请日：2014-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Soo PARK ,  Moosung KIM ,  Taekyun KANG

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/20 ,  G11C5/148 ,  G11C16/30 ,  G11C2207/2227

Abstract: A latch management method of a storage device includes permitting the storage device to enter a reduced power mode in which the storage device operates with a reduced power. The method includes reading initial latch data stored in the at least one nonvolatile memory device in response to the entering operation. The method includes setting latches associated with the at least one nonvolatile memory device based on the read initial latch data.

Abstract translation: 存储装置的锁存管理方法包括允许存储装置进入存储装置以降低的功率运行的降低功率模式。 该方法包括响应于输入操作读取存储在至少一个非易失性存储器件中的初始锁存数据。 该方法包括基于读取的初始锁存数据来设置与至少一个非易失性存储器件相关联的锁存器。

公开(公告)号：US20190130953A1

公开(公告)日：2019-05-02

申请号：US15997964

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun LEE ,  Joon Soo KWON ,  Byung Soo KIM ,  Su-Yong KIM ,  Sang-Soo PARK ,  Il Han PARK ,  Kang-Bin LEE ,  Jong-Hoon LEE ,  Na-Young CHOI

IPC: G11C8/08 ,  G06F3/06 ,  G11C16/12 ,  G11C5/14 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

公开(公告)号：US20180122485A1

公开(公告)日：2018-05-03

申请号：US15625189

申请日：2017-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Soo PARK ,  Jaeyong JEONG

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/30 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/225 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.

公开(公告)号：US20160042803A1

公开(公告)日：2016-02-11

申请号：US14733583

申请日：2015-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Soo KWON ,  Sang-Soo PARK

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621

Abstract: A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage.

Abstract translation: 一种对存储器件进行编程的方法包括：基于第一验证条件将低位编程到包括在字线和位线中的存储单元，该低位属于包含高位的一组位。 第一验证条件基于第一位线电流，用于验证低位编程的第一显影时间和第一字线电压中的至少一个。 该方法包括基于第二验证条件将高位编程到存储器单元。 第二验证条件基于第二位线电流，用于验证高位的编程的第二显影时间和第二字线电压中的至少一个。

公开(公告)号：US20160240223A1

公开(公告)日：2016-08-18

申请号：US15044321

申请日：2016-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hyun KIM ,  Jae-Hyun KIM ,  Byeong-Jun KIM ,  Sang-Soo PARK ,  Jun-Soo LEE ,  Ho-Chul HWANG

IPC: G11B27/031

CPC classification number: G11B27/031

Abstract: The present disclosure provides an electronic device and method for playing image data. The method for playing back image data in an electronic device includes storing an audiovisual (A/V) data for a predetermined period of time in a memory of the electronic device. The electronic device plays back the A/V data, wherein upon playing back, by the electronic device, the A/V data comprises analyzing an audio signal of the A/V data dynamically to select one of a plurality of sound effects based on the analyzed audio signal. The A/V data is played back by applying the selected sound effect to at least a part of the A/V signal.

Abstract translation: 本公开提供了一种用于播放图像数据的电子设备和方法。 用于在电子设备中回放图像数据的方法包括将预定时间段的视听（A / V）数据存储在电子设备的存储器中。 电子设备回放A / V数据，其中，在通过电子设备播放时，A / V数据包括动态地分析A / V数据的音频信号，以基于该信号来选择多个声音效果中的一个 分析音频信号。 通过将选择的声音效果应用于至少一部分A / V信号来播放A / V数据。

公开(公告)号：US20130185609A1

公开(公告)日：2013-07-18

申请号：US13668607

申请日：2012-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Soo PARK ,  Jae-Yong JEONG

IPC: G06F11/07

CPC classification number: G06F11/0751

Abstract: A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.

Abstract translation: 提供非易失性存储器系统。 非易失性存储器件包括多级存储器阵列和页缓冲器; 以及存储器控制器，被配置为控制要从多级存储器阵列读取并存储在页缓冲器中的第一页数据，要检测的第一页数据的第一错误位，存储在第一页数据中的第一页数据的错误 使用在第一误差位中校正的误差的第一校正数据进行校正的页面缓冲器以及要对多级存储器阵列执行的经纠错的第一页数据的第一刷新程序操作。