公开(公告)号：US20160351569A1

公开(公告)日：2016-12-01

申请号：US15164396

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol SONG ,  Moon-kyu PARK ,  Sang-jin HYUN ,  Hu-yong LEE ,  Hoon-joo NA ,  Hye-lan LEE

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/49 ,  H01L27/11 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7848

Abstract: Provided are a semiconductor device in which a multi-threshold voltage is embodied by controlling a work function, and a method of manufacturing the same. The device includes a semiconductor substrate including a first region and a second region, a first active region formed in an upper portion of the first region of the semiconductor substrate, a second active region formed in an upper portion of the second region of the semiconductor substrate, a first gate structure formed on the semiconductor substrate across the first active region, the first gate structure including an interfacial layer, a high-k dielectric layer, a capping metal layer, and a work function metal layer that are stacked sequentially, and a second gate structure formed on the semiconductor substrate across the second active region, the second gate structure including the interfacial layer, the high-k dielectric layer, the capping metal layer, a dielectric layer, and the work function metal layer that are stacked sequentially.

Abstract translation: 提供一种其中通过控制功函数来实现多阈值电压的半导体器件及其制造方法。 该器件包括：半导体衬底，包括第一区域和第二区域;形成在半导体衬底的第一区域的上部的第一有源区;形成在半导体衬底的第二区域的上部的第二有源区; 形成在跨过第一有源区的半导体衬底上的第一栅极结构，第一栅极结构包括依次层叠的界面层，高k电介质层，封盖金属层和功函数金属层，以及 第二栅极结构，形成在半导体衬底上跨越第二有源区，第二栅极结构包括依次层叠的界面层，高k电介质层，封盖金属层，电介质层和功函数金属层。

公开(公告)号：US20160315080A1

公开(公告)日：2016-10-27

申请号：US15001283

申请日：2016-01-20

Applicant: Samsung Electronics Co .. Ltd.

Inventor： Jae-yeol SONG ,  Wan-don KIM ,  Oh-seong KWON ,  Hyeok-jun SON ,  Sang-jin HYUN ,  Hoon-joo NA

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

Abstract translation: 集成电路器件包括包括第一和第二鳍式有源区以及第一和第二栅极结构的衬底。 第一栅极结构包括第一鳍状有源区上的第一栅极绝缘层，以覆盖第一鳍状有源区的上表面和两个侧表面，第一栅极绝缘层上的第一栅电极和第一栅极绝缘层的第一方向上具有第一厚度 垂直于衬底的上表面，以及第一栅电极上的第二栅电极。 第二栅极结构包括在第二鳍状有源区上的第二栅极绝缘层，以覆盖第二鳍状有源区的上表面和两个侧表面，第二栅极绝缘层上的第三栅极绝缘层，第二栅极绝缘层上的第三栅极电极 第三栅极绝缘层，并且具有与第一方向上的第一厚度不同的第二厚度，以及第三栅电极上的第四栅电极。

公开(公告)号：US20190189767A1

公开(公告)日：2019-06-20

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol SONG ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.