公开(公告)号：US11626503B2

公开(公告)日：2023-04-11

申请号：US17393217

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/45

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US11114544B2

公开(公告)日：2021-09-07

申请号：US16552150

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/45

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US10529817B2

公开(公告)日：2020-01-07

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

公开(公告)号：US10079210B2

公开(公告)日：2018-09-18

申请号：US15186825

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-sun Lee ,  Do-hyun Lee ,  Chul-sung Kim ,  Sang-jin Hyun ,  Joon-gon Lee

IPC: H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.

公开(公告)号：US20150093888A1

公开(公告)日：2015-04-02

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/51

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Abstract translation: 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US11955531B2

公开(公告)日：2024-04-09

申请号：US18174902

申请日：2023-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66515 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US11588039B2

公开(公告)日：2023-02-21

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/822 ,  H01L21/84

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US20200098882A1

公开(公告)日：2020-03-26

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong LEE ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L21/822 ,  H01L29/06 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US20180012889A1

公开(公告)日：2018-01-11

申请号：US15697720

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo NA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

公开(公告)号：US09236313B2

公开(公告)日：2016-01-12

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.