公开(公告)号：US09577075B2

公开(公告)日：2017-02-21

申请号：US14460404

申请日：2014-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract translation: 一种制造半导体器件的方法包括形成在第一方向上延伸的预备鳍型有源图案，形成覆盖预备鳍型有源图案的下部的器件隔离图案，形成沿第二方向延伸的栅极结构，以及 跨越预备鳍型有源图案，形成具有第一区域和第二区域的鳍式有源图案，通过选择性外延生长工艺在第二区域上形成预备杂质掺杂图案，并形成杂质 通过使用等离子体掺杂工艺注入杂质的掺杂图案，其中第一区域的上表面处于第一水平，并且第二区域的上表面处于低于第一水平的第二水平。

公开(公告)号：US09825153B2

公开(公告)日：2017-11-21

申请号：US15422907

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.