公开(公告)号：US09991257B2

公开(公告)日：2018-06-05

申请号：US15013969

申请日：2016-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miseon Park ,  Jongryeol Yoo ,  Hyunjung Lee ,  Yong-Suk Tak ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791

Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.

公开(公告)号：US09773908B2

公开(公告)日：2017-09-26

申请号：US15138914

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo Kim ,  Seunghun Lee ,  Sunjung Kim ,  Hyunjung Lee ,  Bonyoung Koo

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7853

Abstract: A semiconductor device can include a substrate and a fin body that protrudes from a surface of the substrate. The fin body can include a lower portion having a first lattice structure and an upper portion, separated from the lower portion by a boundary, the upper portion having a second lattice structure that is different than the first lattice structure. An epitaxially grown epitxial layer can be on the lower and upper portions.

公开(公告)号：US09608114B2

公开(公告)日：2017-03-28

申请号：US14989956

申请日：2016-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Kim ,  Seung Hun Lee ,  Sunjung Kim ,  Hyun Jung Lee ,  Bonyoung Koo

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/7849 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes a buffer layer on a substrate, the buffer layer having a lattice constant different from that of the substrate, a fin structure upwardly protruding from the buffer layer, a gate electrode crossing over the fin structure, a cladding layer at a side of the fin structure and covering a top surface and sidewalls of the fin structure, and an interfacial layer between the cladding layer and the fin structure, the interfacial layer including a same element as the buffer layer.

公开(公告)号：US09508832B2

公开(公告)日：2016-11-29

申请号：US14749037

申请日：2015-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jung Lee ,  Bonyoung Koo ,  Sunjung Kim ,  Jongryeol Yoo ,  Seung Hun Lee ,  Poren Tang

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。

公开(公告)号：US09825153B2

公开(公告)日：2017-11-21

申请号：US15422907

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

公开(公告)号：US10756211B2

公开(公告)日：2020-08-25

申请号：US15379190

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

公开(公告)号：US10043799B2

公开(公告)日：2018-08-07

申请号：US15407598

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Park ,  Sungho Kang ,  Kichul Kim ,  Sunyoung Lee ,  Han Ki Lee ,  Bonyoung Koo

IPC: H01L21/336 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L29/34 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US09577075B2

公开(公告)日：2017-02-21

申请号：US14460404

申请日：2014-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract translation: 一种制造半导体器件的方法包括形成在第一方向上延伸的预备鳍型有源图案，形成覆盖预备鳍型有源图案的下部的器件隔离图案，形成沿第二方向延伸的栅极结构，以及 跨越预备鳍型有源图案，形成具有第一区域和第二区域的鳍式有源图案，通过选择性外延生长工艺在第二区域上形成预备杂质掺杂图案，并形成杂质 通过使用等离子体掺杂工艺注入杂质的掺杂图案，其中第一区域的上表面处于第一水平，并且第二区域的上表面处于低于第一水平的第二水平。

公开(公告)号：US09553190B2

公开(公告)日：2017-01-24

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC: H01L29/772 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US10062754B2

公开(公告)日：2018-08-28

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Bonyoung Koo ,  Seokhoon Kim ,  Chul Kim ,  Kwan Heum Lee ,  Byeongchan Lee ,  Sujin Jung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.