公开(公告)号：US10685957B2

公开(公告)日：2020-06-16

申请号：US16005915

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hyun Choi ,  Yong-Suk Tak ,  Gi-Gwan Park ,  Bon-Young Koo ,  Ki-Yeon Park ,  Won-Oh Seo

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/26 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.

公开(公告)号：US20190333754A1

公开(公告)日：2019-10-31

申请号：US16217339

申请日：2018-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyoung Lee ,  Minjae Kang ,  Se-Yeon Kim ,  Teawon Kim ,  Yong-Suk Tak ,  Sunjung Kim

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/165 ,  C23C16/36 ,  C23C16/455

Abstract: A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed.

公开(公告)号：US20180301452A1

公开(公告)日：2018-10-18

申请号：US16005915

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hyun Choi ,  Yong-Suk Tak ,  Gi-Gwan Park ,  Bon-Young Koo ,  Ki-Yeon Park ,  Won-Oh Seo

IPC: H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/26 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02636 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L23/26 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.

公开(公告)号：US09929160B1

公开(公告)日：2018-03-27

申请号：US15613334

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juri Lee ,  Yong-Suk Tak ,  Sung-Dae Suk ,  Seungmin Song

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.

公开(公告)号：US09559185B2

公开(公告)日：2017-01-31

申请号：US15134906

申请日：2016-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Suk Tak ,  Gyeom Kim ,  Ki-Yeon Park ,  Sung-Hyun Choi ,  Bon-Young Koo

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/6656 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.

Abstract translation: 半导体器件包括：衬底，其包括有源鳍结构，多个栅极结构，每个栅极结构的侧壁上的第一间隔物，以及在第一间隔物的侧壁上的第二间隔物。 主动翅片结构可以在第一方向上延伸并且包括多个活动翅片，相邻的活动翅片由凹部分开。 多个栅极结构中的每一个可以在与第一方向交叉的第二方向上延伸，并且可以覆盖活动鳍片。 第一间隔物可以包括硅碳氮氧化物（SiOCN），并且可以具有第一碳浓度。 第二间隔物可以包括SiOCN，并且可以具有不同于第一碳浓度的第二碳浓度。 半导体器件可以具有低寄生电容和良好的电特性。

公开(公告)号：US20230035916A1

公开(公告)日：2023-02-02

申请号：US17653390

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tea Won Kim ,  Hyung Joon Kim ,  Yong-Suk Tak ,  Yu Rim Kim ,  Kong Soo Lee

IPC: H01L29/786

Abstract: A semiconductor device includes a conductive line that extends in a first direction on a substrate, a first oxide semiconductor layer, including a first crystalline oxide semiconductor material containing a first metal element, on the conductive line, a second oxide semiconductor layer, which is in physical contact with the first oxide semiconductor layer and is connected to the conductive line, on the conductive line, a gate electrode that extends in a second direction, which crosses the first direction, on a side of the second oxide semiconductor layer, and a capacitor structure connected to the second oxide semiconductor layer on the second oxide semiconductor layer and the gate electrode, wherein the second oxide semiconductor layer includes a second crystalline oxide semiconductor material containing the first metal element and second and third metal elements, which are different from the first metal element.

公开(公告)号：US09728644B2

公开(公告)日：2017-08-08

申请号：US15093892

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Suk Tak ,  Jongryeol Yoo ,  Hyun Jung Lee ,  Miseon Park ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

公开(公告)号：US09837500B2

公开(公告)日：2017-12-05

申请号：US15002379

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjung Lee ,  Keumseok Park ,  Jinyeong Joe ,  Yong-Suk Tak

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/785

Abstract: Provided is a semiconductor device. In some examples, the semiconductor device includes an fin active region protruding from a substrate, gate patterns disposed on the fin active region, a source/drain region disposed on the fin active region between the gate patterns, and contact patterns disposed on the source/drain region. The source/drain region may have a protruding middle section, which may form a wave-shaped upper surface of the source/drain region.

公开(公告)号：US09577075B2

公开(公告)日：2017-02-21

申请号：US14460404

申请日：2014-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract translation: 一种制造半导体器件的方法包括形成在第一方向上延伸的预备鳍型有源图案，形成覆盖预备鳍型有源图案的下部的器件隔离图案，形成沿第二方向延伸的栅极结构，以及 跨越预备鳍型有源图案，形成具有第一区域和第二区域的鳍式有源图案，通过选择性外延生长工艺在第二区域上形成预备杂质掺杂图案，并形成杂质 通过使用等离子体掺杂工艺注入杂质的掺杂图案，其中第一区域的上表面处于第一水平，并且第二区域的上表面处于低于第一水平的第二水平。

公开(公告)号：US10861695B2

公开(公告)日：2020-12-08

申请号：US16217339

申请日：2018-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyoung Lee ,  Minjae Kang ,  Se-Yeon Kim ,  Teawon Kim ,  Yong-Suk Tak ,  Sunjung Kim

IPC: H01L21/00 ,  H01L21/02 ,  C23C16/36 ,  C23C16/455 ,  H01L21/28 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed.