公开(公告)号：US11791209B2

公开(公告)日：2023-10-17

申请号：US17971807

申请日：2022-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  Jaekang Koh ,  Tae-Jong Han

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76865

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US11581326B2

公开(公告)日：2023-02-14

申请号：US16913705

申请日：2020-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Jong Han ,  Jaekang Koh ,  Munjun Kim ,  Su Jong Kim ,  Seung-Heon Lee

IPC: H01L27/11573 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

公开(公告)号：US11482453B2

公开(公告)日：2022-10-25

申请号：US16784830

申请日：2020-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  Jaekang Koh ,  Tae-Jong Han

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US11764119B2

公开(公告)日：2023-09-19

申请号：US17672939

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon Lee ,  Jaekang Koh ,  Hyukwoo Kwon ,  Munjun Kim ,  Taejong Han

IPC: H01L23/29 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L23/291 ,  H01L21/0228 ,  H01L23/3185

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

公开(公告)号：US11264294B2

公开(公告)日：2022-03-01

申请号：US16919307

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon Lee ,  Jaekang Koh ,  Hyukwoo Kwon ,  Munjun Kim ,  Taejong Han

IPC: H01L21/02 ,  H01L23/29 ,  H01L23/31

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.