公开(公告)号：US11882691B2

公开(公告)日：2024-01-23

申请号：US17858361

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  ByeongJu Bae

IPC: H01L21/3213 ,  H01L21/033 ,  H10B12/00 ,  H01L21/8234

CPC classification number: H10B12/482 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/823475 ,  H01L21/823481 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/485

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US11791209B2

公开(公告)日：2023-10-17

申请号：US17971807

申请日：2022-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  Jaekang Koh ,  Tae-Jong Han

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76865

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US20230067987A1

公开(公告)日：2023-03-02

申请号：US17729131

申请日：2022-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounghee KIM ,  Jinsub Kim ,  Munjun Kim ,  Junkwan Kim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: A semiconductor device includes: a lower structure including a device and a lower wiring structure; an insulating layer on the lower structure; a via penetrating the insulating layer; a wiring pattern on the insulating layer and the via; and a silicon oxide layer covering the wiring pattern, and including hydrogen, wherein the wiring pattern includes first and second conductive layers, an upper surface protective layer, and a side surface protective layer, wherein the second conductive layer is on the first conductive layer, wherein the upper surface protective layer covers an upper surface of the second conductive layer, and the side surface protective layer covers side surfaces of the first and second conductive layers, and wherein each of the upper surface protective layer and the side surface protective layer includes a metal material having an activation energy higher than that of a metal material of the second conductive layer.

公开(公告)号：US11482453B2

公开(公告)日：2022-10-25

申请号：US16784830

申请日：2020-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  Jaekang Koh ,  Tae-Jong Han

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US20190279988A1

公开(公告)日：2019-09-12

申请号：US16426075

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon LEE ,  Munjun Kim ,  ByeongJu Bae

IPC: H01L27/108 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US11581326B2

公开(公告)日：2023-02-14

申请号：US16913705

申请日：2020-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Jong Han ,  Jaekang Koh ,  Munjun Kim ,  Su Jong Kim ,  Seung-Heon Lee

IPC: H01L27/11573 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

公开(公告)号：US10748908B2

公开(公告)日：2020-08-18

申请号：US16426075

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  ByeongJu Bae

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US10566333B2

公开(公告)日：2020-02-18

申请号：US15160264

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  ByeongJu Bae

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US20250126778A1

公开(公告)日：2025-04-17

申请号：US18768579

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Lee ,  Yeonjin Hwang ,  Munjun Kim ,  Iksoo Kim ,  Junwon Lee ,  Younseok Choi

IPC: H10B12/00

Abstract: An integrated circuit device and a method of manufacturing the same are provided. The integrated circuit device includes: a substrate having a plurality of active regions; a bit line extending on the substrate in a horizontal direction parallel to an upper surface of the substrate; a direct contact electrically connected to a first active region of the plurality of active regions and connected to the bit line; a contact plug electrically connected to a second active region of the plurality of active regions adjacent to the first active region; and an outer insulation spacer between the bit line and the contact plug and overlapping the bit line in a vertical direction perpendicular to the upper surface of the substrate. The outer insulation spacer includes a doped region doped with a metal element.

公开(公告)号：US12211795B2

公开(公告)日：2025-01-28

申请号：US17509636

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinsub Kim ,  Kyoung-Hee Kim ,  Munjun Kim ,  Jun Kwan Kim ,  Woo Choel Noh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.