公开(公告)号：US20200295042A1

公开(公告)日：2020-09-17

申请号：US16889947

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US20190051665A1

公开(公告)日：2019-02-14

申请号：US16165426

申请日：2018-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20230215805A1

公开(公告)日：2023-07-06

申请号：US18114337

申请日：2023-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yewon SHIN ,  Jaesun YUN ,  Seungjun LEE ,  Jongmin LEE

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

公开(公告)号：US20210366829A1

公开(公告)日：2021-11-25

申请号：US16950031

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yewon SHIN ,  Jaesun YUN ,  Seungjun LEE ,  Jongmin LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged m the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

公开(公告)号：US20210151467A1

公开(公告)日：2021-05-20

申请号：US17162526

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20180374867A1

公开(公告)日：2018-12-27

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Kyoil KOO ,  Hoosung CHO ,  Sunyoung KIM ,  Cheol RYOU ,  Jaesun YUN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.