公开(公告)号：US20240371731A1

公开(公告)日：2024-11-07

申请号：US18507549

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin SHIN ,  Heonjong SHIN ,  June Young PARK ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a support member, an active region, source and drain regions, and a gate electrode. The support member may include a substrate insulation layer including separating insulators and a power wire disposed at a space between the separating insulators. The active region may be disposed on the power wire. The source and drain regions may be positioned adjacent to the active region. The gate electrode may be disposed on the active region.

公开(公告)号：US20240234502A9

公开(公告)日：2024-07-11

申请号：US18323715

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo PARK ,  Wookhyun KWON ,  Yeonho PARK ,  Jongmin SHIN ,  Heonjong SHIN ,  Jongmin JUN ,  Kyubong CHOI

IPC: H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

公开(公告)号：US20240274679A1

公开(公告)日：2024-08-15

申请号：US18435168

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin SHIN ,  Junmo PARK ,  Kyubong CHOI

IPC: H01L29/417 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L27/124 ,  H01L27/1266 ,  H01L29/458 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392

Abstract: An integrated circuit device may include a fin-type active structure elongated in a first horizontal direction, a nanosheet stack including nanosheets on the fin-type active structure, a gate structure extending between the nanosheets, a source/drain structure on the fin-type active structure at a position adjacent to the gate structure and facing the nanosheet stack in the first horizontal direction, a vertical separation layer including a silicon layer in contact with a silicide separation layer. The silicide separation layer may be between the source/drain structure and each of the nanosheet stack and the gate structure. The silicon separation layer may be between the silicide separation layer and each of the nanosheet stack and the gate structure. The source/drain structure may include a metal. The gate structure may include at least one sub-gate surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure.

公开(公告)号：US20240136430A1

公开(公告)日：2024-04-25

申请号：US18201878

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20250081526A1

公开(公告)日：2025-03-06

申请号：US18656949

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin SHIN ,  Woncheol JEONG ,  Heonjong SHIN

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device may includes a plurality of device isolation layers extending lengthwise in a first horizontal direction, a plurality of gap-fill insulation layers arranged apart from one another in the first horizontal direction, a plurality of gate structures extending lengthwise in a second horizontal direction perpendicular to the first horizontal direction and on the plurality of gap-fill insulation layers, a first source/drain region and a second source/drain region respectively disposed at both sides of a first gate structure among the plurality of gate structures with respect to the first horizontal direction, an insulation block under the first source/drain region, and an insulation barrier between the first source/drain region and the insulation block. The insulation barrier may cover a lower surface of the first source/drain region.

公开(公告)号：US20240136398A1

公开(公告)日：2024-04-25

申请号：US18323715

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo PARK ,  Wookhyun KWON ,  Yeonho PARK ,  Jongmin SHIN ,  Heonjong SHIN ,  Jongmin JUN ,  Kyubong CHOI

IPC: H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

公开(公告)号：US20240321689A1

公开(公告)日：2024-09-26

申请号：US18441327

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juneyoung PARK ,  Heonjong SHIN ,  Jongmin SHIN ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including an active device layer including a plurality of source/drain patterns, a plurality of insulating layers on the active device layer, a back end of line (BEOL) structure on the plurality of insulating layers and configured to supply electric power to the active device layer, an intermediate layer between the plurality of insulating layers and the BEOL structure, and at least one power via penetrating through the intermediate layer and at least a part in each of the plurality of insulating layers in a vertical direction. The at least one power via electrically connects the BEOL structure and the active device layer. At least a part of a side surface of the at least one power via is in contact with the intermediate layer.

公开(公告)号：US20240234558A9

公开(公告)日：2024-07-11

申请号：US18201878

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.