公开(公告)号：US20240321873A1

公开(公告)日：2024-09-26

申请号：US18429611

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Juneyoung PARK ,  Jaeran JANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5226

Abstract: An integrated circuit device, including a substrate having a plurality of device regions extending in a first horizontal direction, a plurality of gate electrodes on the plurality of device regions extending in a second horizontal direction that is orthogonal to the first horizontal direction, a plurality of source/drain regions between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes, the plurality of source/drain regions being on portions of the plurality of device regions, a plurality of gate cut regions cutting the plurality of gate electrodes and extending in the first horizontal direction, and a plurality of contact structures including a plurality of contact body portions and a plurality of contact finger portions, the plurality of contact body portions filling the plurality of gate cut regions and extending in the first horizontal direction.

公开(公告)号：US20250096133A1

公开(公告)日：2025-03-20

申请号：US18645765

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo NAM ,  Heonjong SHIN ,  Juneyoung PARK ,  Sanghee LEE

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a plurality of nanosheets facing a fin top of the fin-type active region, a gate line on the fin-type active region, the gate line surrounding each of the nanosheets and extending in a second horizontal direction, and a source/drain region on the fin-type active region. The gate line includes a main gate portion on the nanosheet stack, a first sub gate portion, a second sub gate portion, and a third sub gate portion. A width of the first sub gate portion in the first horizontal direction is greater than or equal to a width of the third sub gate portion in the first horizontal direction and the width of the first sub gate portion is less than a width of the second sub gate portion in the first horizontal direction.

公开(公告)号：US20240321689A1

公开(公告)日：2024-09-26

申请号：US18441327

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juneyoung PARK ,  Heonjong SHIN ,  Jongmin SHIN ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including an active device layer including a plurality of source/drain patterns, a plurality of insulating layers on the active device layer, a back end of line (BEOL) structure on the plurality of insulating layers and configured to supply electric power to the active device layer, an intermediate layer between the plurality of insulating layers and the BEOL structure, and at least one power via penetrating through the intermediate layer and at least a part in each of the plurality of insulating layers in a vertical direction. The at least one power via electrically connects the BEOL structure and the active device layer. At least a part of a side surface of the at least one power via is in contact with the intermediate layer.