公开(公告)号：US20240324193A1

公开(公告)日：2024-09-26

申请号：US18515449

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MinKyung KIM ,  Hakseon Kim ,  Sunggil Kim ,  Jumi Bak ,  Kang-Oh Yun ,  Dongjin Lee ,  Sohyun Lee ,  Junhee Lim

IPC: H10B41/35 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/35 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06524

Abstract: A semiconductor device includes a substrate, a doped region on the substrate, the doped region including impurities of a first conductivity type at a first concentration, a gate structure on the substrate, and a first contact electrically connected to the doped region, the first contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including poly silicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type at a second concentration higher than the first concentration.

公开(公告)号：US20240098996A1

公开(公告)日：2024-03-21

申请号：US18317274

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong Yang ,  Sunggil Kim ,  Yuyeon Kim ,  Jumi Bak

IPC: H10B43/27 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2924/1431

Abstract: A three-dimensional semiconductor memory device may include a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure. The cell array structure may include a stack that includes interlayer insulating layers and conductive patterns alternately stacked with one another, a source structure on the stack, and a vertical structure that extends in the stack and is electrically connected to a bottom surface of the source structure. The vertical structure may include a channel layer that includes first portions respectively in vertical channel holes extending in the stack, and a second portion that extends in a region between the stack and the source structure and is electrically connected to the first portions.