公开(公告)号：US20250017009A1

公开(公告)日：2025-01-09

申请号：US18442229

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong Yang ,  Yuyeon Kim ,  Chaeho Kim

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

Abstract: A semiconductor device includes a gate stacking structure, a channel structure, and a horizontal conductive layer. The gate stacking structure may include a plurality of gate electrodes and a plurality of insulation layers that are alternately stacked. The channel structure may be provided with an inner portion extending into the gate stacking structure and a protruded portion that protrudes from one surface of the gate stacking structure. The horizontal conductive layer may be connected to the protruded portion of the channel structure. In this case, the channel structure may include a semiconductor layer. The semiconductor layer may include a polycrystalline region in at least the protruded portion and including a polycrystalline semiconductor material and in a channel region positioned in the inner portion and having a crystal structure different from a crystal structure of the polycrystalline region.

公开(公告)号：US20250015182A1

公开(公告)日：2025-01-09

申请号：US18444592

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeong Yang ,  Yuyeon Kim ,  Jaeho Jung

IPC: H01L29/78 ,  H01L25/065 ,  H01L29/66 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00

Abstract: A semiconductor device includes a gate stacking structure that includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked with each other, and a plurality of channel structures that penetrate the gate stacking structure. The plurality of channel structures include a first channel structure that includes a first channel layer, and a plurality of second channel structures adjacent to the first channel structure and that include a plurality of second channel layers. The first channel layer in the first channel structure and the plurality of second channel layers in the plurality of second channel structures have a same crystal orientation.

公开(公告)号：US20240098996A1

公开(公告)日：2024-03-21

申请号：US18317274

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong Yang ,  Sunggil Kim ,  Yuyeon Kim ,  Jumi Bak

IPC: H10B43/27 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2924/1431

Abstract: A three-dimensional semiconductor memory device may include a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure. The cell array structure may include a stack that includes interlayer insulating layers and conductive patterns alternately stacked with one another, a source structure on the stack, and a vertical structure that extends in the stack and is electrically connected to a bottom surface of the source structure. The vertical structure may include a channel layer that includes first portions respectively in vertical channel holes extending in the stack, and a second portion that extends in a region between the stack and the source structure and is electrically connected to the first portions.

公开(公告)号：US20240404854A1

公开(公告)日：2024-12-05

申请号：US18633117

申请日：2024-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Jung ,  Yuyeon Kim ,  Siyeong Yang

IPC: H01L21/673 ,  H01L21/67

Abstract: The present disclosure relates to substrate processing apparatuses and substrate processing methods. An example substrate processing apparatus comprises an outer chamber that provides an internal space, a process tube in the outer chamber, a heater between the outer chamber and the process tube, and a boat inserted into the process tube. The boat includes a plurality of substrate support devices that are vertically stacked. Each substrate support device of the plurality of substrate support devices includes a support member that supports a substrate, a lower electrode below the support member, and an upper electrode above the support member and spaced apart from the support member.