公开(公告)号：US20230215926A1

公开(公告)日：2023-07-06

申请号：US17930145

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jaeung Koo ,  Boun Yoon ,  Ilyoung Yoon ,  Kangchun Lee ,  Seungjae Lee ,  Junhwan Yim ,  Huiteak Hong

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42392

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.