公开(公告)号：US20230215926A1

公开(公告)日：2023-07-06

申请号：US17930145

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jaeung Koo ,  Boun Yoon ,  Ilyoung Yoon ,  Kangchun Lee ,  Seungjae Lee ,  Junhwan Yim ,  Huiteak Hong

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42392

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.

公开(公告)号：US20220310594A1

公开(公告)日：2022-09-29

申请号：US17569363

申请日：2022-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youncheol Jeong ,  Jaeung Koo ,  Kwansung Kim ,  Seungyoon Kim ,  Boun Yoon ,  Jooho Jung ,  Sukbae Joo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure vertically overlapping the active region and the plurality of channel layers on the substrate, extending in a second direction, and including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on an upper surface of the gate electrode, a first source/drain region disposed on a side of the gate structure on the active region and in contact with the plurality of channel layers, an isolation structure intersecting the active region on the substrate, extending in the second direction, and disposed between the first source/drain region and a second source/drain region adjacent to each other, and contact structures in contact with the source/drain regions.

公开(公告)号：US11094586B2

公开(公告)日：2021-08-17

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon Choi ,  Jaeung Koo ,  Kwansung Kim ,  Bo Yun Kim ,  Wandon Kim ,  Boun Yoon ,  Jeonghyuk Yim ,  Yeryung Jeon

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3105

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.