公开(公告)号：US12278168B1

公开(公告)日：2025-04-15

申请号：US18886289

申请日：2024-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongsuk Oh ,  Jaemyung Choi ,  Kang-Ill Seo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L29/417

Abstract: Provided is a semiconductor device including a base layer and an interconnect structure on the base layer, the interconnect structure including: a 1st metal line on the base layer; a 1st top via vertically protruded from the 1st metal line without a connection surface therebetween; an isolation layer on the 1st metal line and the 1st top via; and a planarization stop layer vertically and laterally on the isolation layer.

公开(公告)号：US20250025981A1

公开(公告)日：2025-01-23

申请号：US18647240

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojoon Lee ,  Jinuk Byun ,  Joongsuk Oh ,  Seongryeol Kim ,  Younggu Kim ,  Seunghoon Choi ,  Jaemyung Choe

IPC: B24B37/005

Abstract: The present disclosure relates to devices, methods, and systems for transforming measurement data. An example device for transforming measurement data includes a communicator configured to receive first measurement data, the first measurement data including step height values on a semiconductor chip with a chemical mechanical polishing (CMP) process performed thereon, and to receive layout data comprising a layout included in the semiconductor chip, and a processor configured to, based on the layout data, transform the first measurement data to second measurement data, the second measurement data including step height values of the semiconductor chip with a metal deposited thereon.

公开(公告)号：US20250022713A1

公开(公告)日：2025-01-16

申请号：US18633627

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jinuk Byun ,  Hoyoung Kim ,  Hyunkyu Moon ,  Kiho Bae ,  Boun Yoon ,  Hojoon Lee ,  Seunghoon Choi

IPC: H01L21/304 ,  G06N3/04 ,  H01L21/66 ,  H01L21/67

Abstract: An offset data correction method includes measuring a measurement target that has undergone a chemical mechanical polishing (CMP) process, generating an offset correction model based on the measurement of the measurement target, and using the offset correction model, correcting measured data obtained from the measurement of the measurement target, wherein the offset correction model is trained by using the measured data and layout data of the measurement target as inputs.

公开(公告)号：US20230215926A1

公开(公告)日：2023-07-06

申请号：US17930145

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jaeung Koo ,  Boun Yoon ,  Ilyoung Yoon ,  Kangchun Lee ,  Seungjae Lee ,  Junhwan Yim ,  Huiteak Hong

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42392

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.