公开(公告)号：US20240341086A1

公开(公告)日：2024-10-10

申请号：US18622473

申请日：2024-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/50

Abstract: An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.

公开(公告)号：US20230215926A1

公开(公告)日：2023-07-06

申请号：US17930145

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jaeung Koo ,  Boun Yoon ,  Ilyoung Yoon ,  Kangchun Lee ,  Seungjae Lee ,  Junhwan Yim ,  Huiteak Hong

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42392

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.

公开(公告)号：US20240155830A1

公开(公告)日：2024-05-09

申请号：US18413434

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H10B12/00

CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US11910594B2

公开(公告)日：2024-02-20

申请号：US17859247

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H10B12/00

CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US11757015B2

公开(公告)日：2023-09-12

申请号：US17196321

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghoon Choi ,  Ilyoung Yoon ,  Ilsu Park ,  Kiho Bae ,  Boun Yoon ,  Yooyong Lee

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/823443 ,  H01L21/823475 ,  H01L29/42372

Abstract: A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

公开(公告)号：US20210134806A1

公开(公告)日：2021-05-06

申请号：US16903040

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US09006067B2

公开(公告)日：2015-04-14

申请号：US14146185

申请日：2014-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Kyeong Kang ,  Jaeseok Kim ,  Boun Yoon ,  Hoyoung Kim ,  Ilyoung Yoon

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

公开(公告)号：US20250038110A1

公开(公告)日：2025-01-30

申请号：US18663344

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Youngtae Kim ,  Ilyoung Yoon

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate having a front side and a back side opposite to the front side and including a fin-type active region in the front side and a substrate recess in the back side, an isolation film in the substrate defining the fin-type active region, a source/drain region on the fin-type active region, a contact plug above the substrate, a backside power rail at least partially filling the substrate recess, and a via power rail electrically connected to the contact plug, the via power rail extending into the isolation film and connected to the backside power rail. A side surface of the backside power rail and a side surface of the via power rail form an obtuse angle at a portion where the backside power rail is connected to the via power rail.

公开(公告)号：US20230201887A1

公开(公告)日：2023-06-29

申请号：US17947242

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjin Kim ,  Kiho Bae ,  Boun Yoon ,  Ilyoung Yoon

IPC: B08B3/12 ,  B08B1/04 ,  B08B3/08

CPC classification number: B08B3/12 ,  B08B1/04 ,  B08B3/08

Abstract: A substrate cleaning device, includes: a substrate cleaning module including first and second roll members adjacent to lower and upper surfaces of a substrate, respectively, first and second driving units configured to move the first and second roll members, a first roll cleaning module including a roll receiving region, a first cleaning solution supply unit supplying a first cleaning solution, and an ultrasonic generating unit applying ultrasonic vibrations; a second roll cleaning module including a housing, a brush pad in the housing, and a second cleaning solution supply unit supplying a second cleaning solution; and a control unit controlling the first driving unit so that the first roll member contacts the substrate lower surface or is accommodated in the roll receiving region, and to control the second driving unit so that the second roll member contacts the substrate upper surface or is seated on the brush pad.

公开(公告)号：US11411004B2

公开(公告)日：2022-08-09

申请号：US16903040

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.