公开(公告)号：US20250142956A1

公开(公告)日：2025-05-01

申请号：US18659726

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  JUNG HAN LEE ,  KWANYOUNG CHUN ,  Kwangmuk LEE

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed is a three-dimensional semiconductor device comprising a substrate including first and second regions, a first active section on the first region and including a first lower channel pattern and a first lower source/drain pattern, a second active section on the first active section and including a first upper channel pattern and a first upper source/drain pattern, a third active section on the second region and including a second lower channel pattern and a second lower source/drain pattern, a fourth active section on the third active section and including a second upper channel pattern and a second upper source/drain pattern, and a gate electrode on the first and second lower channel patterns and the first and second upper channel patterns. A first width in a first direction of the first lower channel pattern is greater than a second width in the first direction of the second lower channel pattern.

公开(公告)号：US20180130786A1

公开(公告)日：2018-05-10

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHARMA DEEPAK ,  RAJEEV RANJAN ,  KUCHANURI SUBHASH ,  CHULHONG PARK ,  JAESEOK YANG ,  KWANYOUNG CHUN

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US20210165946A1

公开(公告)日：2021-06-03

申请号：US17034634

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGKYU CHAE ,  JINWOO JEONG ,  KWANYOUNG CHUN

IPC: G06F30/392 ,  G06F30/3312

Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.

公开(公告)号：US20170229478A1

公开(公告)日：2017-08-10

申请号：US15496015

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

IPC: H01L27/118 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

公开(公告)号：US20150179646A1

公开(公告)日：2015-06-25

申请号：US14504075

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。