公开(公告)号：US11069776B2

公开(公告)日：2021-07-20

申请号：US16789498

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Namkyu Cho ,  Seokhoon Kim ,  Kang Hun Moon ,  Hyun-Kwan Yu ,  Sihyung Lee

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

公开(公告)号：US20190393347A1

公开(公告)日：2019-12-26

申请号：US16213186

申请日：2018-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG WOO KIM ,  Do Hee Kim ,  Hyo Jin Kim ,  Kang Hun Moon ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

公开(公告)号：US10068993B2

公开(公告)日：2018-09-04

申请号：US15871479

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US09853160B2

公开(公告)日：2017-12-26

申请号：US15135566

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US10700203B2

公开(公告)日：2020-06-30

申请号：US16213186

申请日：2018-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Woo Kim ,  Do Hee Kim ,  Hyo Jin Kim ,  Kang Hun Moon ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L27/088

Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

公开(公告)号：US10319859B2

公开(公告)日：2019-06-11

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20240063262A1

公开(公告)日：2024-02-22

申请号：US18127298

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Uk Jeon ,  Kyung Ho Kim ,  Ki Hwan Kim ,  Kang Hun Moon ,  Cho Eun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66553 ,  H01L27/092

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.

公开(公告)号：US11569350B2

公开(公告)日：2023-01-31

申请号：US17371858

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Namkyu Cho ,  Seokhoon Kim ,  Kang Hun Moon ,  Hyun-Kwan Yu ,  Sihyung Lee

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

公开(公告)号：US09905676B2

公开(公告)日：2018-02-27

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US10128112B2

公开(公告)日：2018-11-13

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun Lee ,  Jin Bum Kim ,  Kang Hun Moon ,  Jae Myung Choe ,  Sun Jung Kim ,  Dong Suk Shin ,  Il Gyou Shin ,  Jeong Ho Yoo

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/223 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.