公开(公告)号：US09177891B2

公开(公告)日：2015-11-03

申请号：US14045648

申请日：2013-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/52 ,  H01L23/48 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US20160056296A1

公开(公告)日：2016-02-25

申请号：US14931490

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US20150228796A1

公开(公告)日：2015-08-13

申请号：US14695672

申请日：2015-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

公开(公告)号：US09893190B2

公开(公告)日：2018-02-13

申请号：US15494845

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US20170229581A1

公开(公告)日：2017-08-10

申请号：US15494845

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US09640665B2

公开(公告)日：2017-05-02

申请号：US14931490

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US09536868B2

公开(公告)日：2017-01-03

申请号：US14875385

申请日：2015-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/48 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US09196733B2

公开(公告)日：2015-11-24

申请号：US14695672

申请日：2015-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。