公开(公告)号：US09893190B2

公开(公告)日：2018-02-13

申请号：US15494845

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US08906757B2

公开(公告)日：2014-12-09

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US09640665B2

公开(公告)日：2017-05-02

申请号：US14931490

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US09196733B2

公开(公告)日：2015-11-24

申请号：US14695672

申请日：2015-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

公开(公告)号：US20150076617A1

公开(公告)日：2015-03-19

申请号：US14548871

申请日：2014-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L27/088 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20130143372A1

公开(公告)日：2013-06-06

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Myeong-Cheol KIM ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

公开(公告)号：US20180331201A1

公开(公告)日：2018-11-15

申请号：US16026749

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

公开(公告)号：US09536825B2

公开(公告)日：2017-01-03

申请号：US14712136

申请日：2015-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Wei-Hua Hsu ,  Choong-Ho Lee ,  Hyung-Jong Lee

IPC: H01L21/70 ,  H01L23/522 ,  H01L27/092 ,  H01L27/088 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor. The first contact includes a first work function control layer having a first thickness and a first conductive layer formed on the first work function control layer, the second contact includes a second work function control layer having a second thickness different from the first thickness and a second conductive layer formed on the second work function control layer, and the first contact and the second contact have different work functions.

Abstract translation: 提供半导体器件及其制造方法。 该半导体器件包括分别包括第一区域和第二区域的基板，分别形成在第一区域和第二区域上的第一晶体管和第二晶体管，形成在第一晶体管上的第一触点和形成在第一晶体管上的第二触点 第二晶体管。 第一触点包括具有第一厚度的第一功函数控制层和形成在第一功函数控制层上的第一导电层，第二触点包括具有不同于第一厚度的第二厚度的第二功函数控制层， 导电层形成在第二功函数控制层上，第一触点和第二触点具有不同的功能。