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公开(公告)号：US10193060B2
公开(公告)日：2019-01-29
申请号：US15449538
申请日：2017-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoon-Sung Han , Ki-Seok Suh , Woo-Jin Kim
Abstract: An MRAM device may include an insulating interlayer structure, a lower electrode contact structure and a variable resistance structure. The insulating interlayer may be formed on a substrate. The lower electrode contact structure may extend through the insulating interlayer. The lower electrode contact structure may include a first electrode having a pillar shape and a second electrode having a cylindrical shape on the first electrode. An upper surface of the second electrode may have a ring shape. A variable resistance structure may be formed on the second electrode. The variable resistance structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode sequentially stacked.
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公开(公告)号：US09324382B2
公开(公告)日：2016-04-26
申请号：US14510629
申请日：2014-10-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ki-Seok Suh , Jae-kyu Lee
CPC classification number: G11C5/08 , G11C5/063 , G11C11/16 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C13/0023 , G11C2213/71 , H01L27/228
Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.
Abstract translation: 电阻式存储器件包括具有多个单元存储器单元的单元块，其中电阻元件和单元选择元件串联连接在一起，所述单元块响应于字线，位线和 源极线和虚拟线，当不同的互连层分别形成源极线和位线时，分别与形成在源极线的互连层之间的剩余互连层的下侧形成的互连层之一连接， 位线，其中虚线具有比下互连层的电阻低的电阻。
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公开(公告)号：US09281344B2
公开(公告)日：2016-03-08
申请号：US14599064
申请日：2015-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-kyu Lee , Ki-Seok Suh
CPC classification number: H01L27/228 , G11C11/1659 , H01L43/02 , H01L43/08
Abstract: The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.
Abstract translation: 磁存储器件包括沿与第一方向正交的第二方向平行布置的多条源极线，同时在衬底上沿第一方向延伸;多条字线，沿第一方向平行布置，同时沿第二方向延伸 在所述基板上，沿着所述第一方向在所述基板上沿所述第一方向延伸而与所述多个源极线交替的多个位线，所述多个位线在所述第二方向上平行布置，并且所述多个有源区域被布置成相对于 所述第一方向被布置成使得当所述多条字线中的一条字线和所述多条源极线或多条位线中的一条被选择时选择一个存储器单元。
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公开(公告)号：US10008539B2
公开(公告)日：2018-06-26
申请号：US15234257
申请日：2016-08-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Kyu Lee , Sung-In Kim , Ki-Seok Suh
CPC classification number: H01L27/228 , G11C11/1655 , G11C11/1659
Abstract: A magnetoresistive random access memory (MRAM) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction; a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure.
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