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公开(公告)号：US20190088524A1
公开(公告)日：2019-03-21
申请号：US15964294
申请日：2018-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee , Seung Hwan LEE
IPC: H01L21/683 , H01L21/56 , H01L21/78 , H01L23/544 , H01L23/31
CPC classification number: H01L21/6835 , H01L21/568 , H01L21/78 , H01L23/3121 , H01L23/544 , H01L2221/68381 , H01L2223/54433
Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.
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公开(公告)号：US20230005872A1
公开(公告)日：2023-01-05
申请号：US17844453
申请日：2022-06-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongkwan Kim , Kunsil Lee
Abstract: A semiconductor package includes: a first substrate; a second substrate including a semiconductor element formed thereon; a film layer between the first substrate and the second substrate; and a molding member surrounding the second substrate, wherein the film layer includes a crystalline spherical silica filler distributed in a matrix.
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公开(公告)号：US20170358558A1
公开(公告)日：2017-12-14
申请号：US15475650
申请日：2017-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee
IPC: H01L25/065 , H01L23/48 , H01L25/00
CPC classification number: H01L25/0657 , H01L23/481 , H01L25/50 , H01L2224/16145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2225/06593
Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
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公开(公告)号：US11935868B2
公开(公告)日：2024-03-19
申请号：US17384046
申请日：2021-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee , Dongkwan Kim
IPC: H01L25/065 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/32 , H01L24/73 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517
Abstract: A semiconductor package is disclosed. The semiconductor package includes a base structure, a first semiconductor chip over the base structure, a second semiconductor chip over the first semiconductor chip, an adhesive layer between the first semiconductor chip and the second semiconductor chip, and a molding layer covering the first semiconductor chip, the second semiconductor chip and the adhesive layer, and including an interposition portion interposed between the base structure and the first semiconductor chip.
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公开(公告)号：US10256215B2
公开(公告)日：2019-04-09
申请号：US15927373
申请日：2018-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee
IPC: H01L23/02 , H01L23/22 , H01L25/065 , H01L23/48 , H01L25/00
Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
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Patent Agency Ranking
公开(公告)号：US20180211937A1
公开(公告)日：2018-07-26
申请号：US15927373
申请日：2018-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee
IPC: H01L25/065 , H01L25/00 , H01L23/48
CPC classification number: H01L25/0657 , H01L23/481 , H01L25/50 , H01L2224/16145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2225/06593
Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
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公开(公告)号：US10825710B2
公开(公告)日：2020-11-03
申请号：US15964294
申请日：2018-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee , Seung Hwan Lee
IPC: H01L21/683 , H01L21/56 , H01L23/544 , H01L23/31 , H01L21/78
Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.
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公开(公告)号：US10665571B2
公开(公告)日：2020-05-26
申请号：US16298083
申请日：2019-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee
IPC: H01L23/02 , H01L23/22 , H01L25/065 , H01L23/48 , H01L25/00
Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
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公开(公告)号：US09941252B2
公开(公告)日：2018-04-10
申请号：US15475650
申请日：2017-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kunsil Lee
CPC classification number: H01L25/0657 , H01L23/481 , H01L25/50 , H01L2224/16145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2225/06593
Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
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公开(公告)号：US11908727B2
公开(公告)日：2024-02-20
申请号：US17671022
申请日：2022-02-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kunsil Lee , Seung Hwan Lee
IPC: H01L21/683 , H01L21/56 , H01L23/544 , H01L23/31 , H01L21/78
CPC classification number: H01L21/6835 , H01L21/568 , H01L21/78 , H01L23/3121 , H01L23/544 , H01L2221/68381 , H01L2223/54433
Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.
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