公开(公告)号：US20190199335A1

公开(公告)日：2019-06-27

申请号：US16036030

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob CHAE ,  Jong-Ryun CHOI

IPC: H03K5/156 ,  H03K5/133 ,  H03K5/135 ,  G01R31/317

CPC classification number: H03K5/1565 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/31727 ,  H03K5/133 ,  H03K5/135

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

公开(公告)号：US20190190505A1

公开(公告)日：2019-06-20

申请号：US16039050

申请日：2018-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin Young YI ,  Kwan Yeob CHAE

IPC: H03K5/131 ,  H03K5/14 ,  H03K5/135 ,  H03H11/26

CPC classification number: H03K5/131 ,  H03H11/265 ,  H03K5/135 ,  H03K5/14 ,  H03K2005/00071

Abstract: A delay control circuit includes: a first step delay cell including a first switch having a first end connected to a first node, and a first capacitor connected to a second end of the first switch; a second step delay cell including a second switch having a first end connected to a second node, and a second capacitor connected to a second end of the second switch; and a first inverter configured to couple an output signal of the first step delay cell to an input of the second step delay cell, wherein the first switch and the second switch are turned on and off by a same control signal.

公开(公告)号：US20200373919A1

公开(公告)日：2020-11-26

申请号：US16989074

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob CHAE ,  Jong-Ryun CHOI

IPC: H03K5/156 ,  G01R31/317 ,  H03K5/135 ,  H03K5/133

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

公开(公告)号：US20170092344A1

公开(公告)日：2017-03-30

申请号：US15264946

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob CHAE ,  Hyun-Hyuck KIM ,  Sang Hune PARK ,  Shin Young YI ,  Won LEE

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G06F13/4243 ,  G11C7/22

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.