公开(公告)号：US20230402074A1

公开(公告)日：2023-12-14

申请号：US18166737

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok BAEK ,  Hye-Ran KIM ,  Min Ho MAEING ,  SungYong CHO ,  MoonChul CHOI

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/52

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C29/52

Abstract: Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.