公开(公告)号：US20240289018A1

公开(公告)日：2024-08-29

申请号：US18386855

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran KIM ,  Taeyoung OH

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0673 ,  G06F11/1076

Abstract: A memory device includes: a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers further is configured to sample a corresponding first CA signal among the plurality of first CA signals; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers.

公开(公告)号：US20170110169A1

公开(公告)日：2017-04-20

申请号：US15187967

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran KIM ,  Tae-Young OH

IPC: G11C7/22 ,  G11C7/12

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/12 ,  G11C2207/2254

Abstract: A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.

公开(公告)号：US20220270662A1

公开(公告)日：2022-08-25

申请号：US17536537

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Seok KANG ,  Sun Young KIM ,  Hye-Ran KIM ,  Tae-Yoon LEE ,  Sung Yong CHO

IPC: G11C11/406 ,  G06F3/06

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

公开(公告)号：US20170110165A1

公开(公告)日：2017-04-20

申请号：US15298491

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran KIM ,  Tae-Young OH

IPC: G11C7/22 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.

公开(公告)号：US20230402074A1

公开(公告)日：2023-12-14

申请号：US18166737

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok BAEK ,  Hye-Ran KIM ,  Min Ho MAEING ,  SungYong CHO ,  MoonChul CHOI

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/52

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C29/52

Abstract: Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.