公开(公告)号：US10923407B2

公开(公告)日：2021-02-16

申请号：US15630934

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/485 ,  H01L21/822 ,  H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US10559543B2

公开(公告)日：2020-02-11

申请号：US16024309

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/31

Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

公开(公告)号：US10916509B2

公开(公告)日：2021-02-09

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sundae Kim ,  Hyunggil Baek ,  Namgyu Baek ,  Seunghun Shin ,  Donghoon Won

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/02 ,  H01L23/58

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20190164915A1

公开(公告)日：2019-05-30

申请号：US16024309

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek

IPC: H01L23/58 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

公开(公告)号：US10418335B2

公开(公告)日：2019-09-17

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sundae Kim ,  Hyunggil Baek ,  Namgyu Baek ,  Seunghun Shin ,  Donghoon Won

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/78 ,  H01L23/58

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US09716048B2

公开(公告)日：2017-07-25

申请号：US14985379

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.