公开(公告)号：US20220130884A1

公开(公告)日：2022-04-28

申请号：US17393855

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Shik KIM ,  Min-Sun KEEL ,  Hoon Joo NA ,  Kang Ho LEE ,  Kil Ho LEE ,  Sang Kil LEE ,  Jung Hyuk LEE ,  Shin Hee HAN

IPC: H01L27/146

Abstract: An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.

公开(公告)号：US20210098043A1

公开(公告)日：2021-04-01

申请号：US17106242

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Kil LEE

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  G11C14/00 ,  H01L43/02

Abstract: A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

公开(公告)号：US20220139991A1

公开(公告)日：2022-05-05

申请号：US17368112

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Shik KIM ,  Min-Sun KEEL ,  Sang Kil LEE

IPC: H01L27/146 ,  H01L25/065 ,  H01L27/22

Abstract: An image sensor includes an upper chip having a pixel array connected to a first connecting structure, and a lower chip below the upper chip and having a second connecting structure connected to the first connecting structure and having first and second stacked metal layers with a same thickness, a third metal layer on the second metal layer and thicker than the second metal layer, a fourth metal layer on the third metal layer and thicker than the third metal layer, first through third insulating layers alternating with the first through fourth metal layers, a first memory device with a first MTJ element in at least one of the first and second insulating layers, and a second memory device with a second MTJ element different from the first MTJ element, the second MTJ element being in at least one of the first through third insulating layers.